Commit graph

62498 commits

Author SHA1 Message Date
Ley Foon Tan
594cacf063 arm: socfpga: agilex: Add SPL for Agilex SoC
Add SPL support for Agilex SoC.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
1560357dec board: intel: agilex: Add socdk board support for Intel Agilex SoC
Add socdk board support for Intel Agilex SoC

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
6a48c34c25 ddr: altera: agilex: Add SDRAM driver for Agilex
Add SDRAM driver for Agilex SoC.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
733cc6cbcc ddr: altera: Restructure Stratix 10 SDRAM driver
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
a6e5b06bea arm: agilex: Add clock handoff offset for Agilex
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
fec7ddc190 cache: Add Arteris Ncore cache coherent unit driver
Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.

Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
b4a20cb300 arm: socfpga: agilex: Add clock wrapper functions
Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
c168fc71a3 clk: agilex: Add clock driver for Agilex
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
20322cea64 arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
38229994af arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move Stratix10 and Agilex clock manager common code to new header file.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
975f66bb57 arm: socfpga: agilex: Add system manager support
Add system manager support for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
2fd1dc5593 arm: socfpga: Move Stratix10 and Agilex system manager common code
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
50278d4ade arm: socfpga: agilex: Add reset manager support
Add reset manager support for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
fd5374aa29 arm: socfpga: Move Stratix10 and Agilex reset manager common code
Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.

Remove unused RSTMGR_XXX defines.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
8b7962a349 arm: socfpga: Move firewall code to firewall file
Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.

SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
2145e611fc arm: socfpga: agilex: Add base address for Intel Agilex SoC
Add base address for Intel Agilex SoC.

Reuse base_addr_s10.h for Agilex, only one base address is
different from S10.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
94172c7961 arm: socfpga: Convert clock manager from struct to defines
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get clock manager base address from DT node instead of using
#define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
db5741f7a8 arm: socfpga: Convert system manager from struct to defines
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get system manager base address from DT node instead of
using #define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
bb25aca134 arm: socfpga: Convert reset manager from struct to defines
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get reset manager base address from DT node instead of using
#define.

spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
dd72cbd9e9 arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
In preparation to get base address from DT.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
5c9c71b660 spl: Allow cache drivers to be used in SPL
Add an option for building cache drivers in SPL.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Andy Shevchenko
3a117e721c x86: edison: Enable DFU timeout
The stock U-Boot on Intel Edison has timeout parameter for DFU command.
Enable it here to be compatible with the original U-Boot configuration.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-01-07 14:37:50 +01:00
Andy Shevchenko
98a8f445fd dfu: Add optional timeout parameter
When the `dfu` command is called from the U-Boot environment,
it now accepts an optional parameter that specifies a timeout (in seconds).
If a DFU connection is not made within that time the `dfu` command exits
(as it would if Ctrl+C was pressed). If the timeout is left empty or being
zero the `dfu` command behaves as it does now.

This is useful for allowing U-Boot to check to see if anything wants to
upload new firmware before continuing to boot.

The patch is based on the commit
5e966ccc3c
by Sebastien Colleur, which has been heavily reworked due to U-Boot changes
in the past.

Signed-off-by: Brad Campbell <bradjc5@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-01-07 14:37:50 +01:00
Andy Shevchenko
2b1f8c2bdf dfu: Refactor do_dfu() to handle optional argument
In the future we may utilize optional argument in 'dfu' command line.
As a preparation for this, refactor do_dfu().

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2020-01-07 14:37:50 +01:00
Andy Shevchenko
fdba54ea2f dfu: Drop unused prototype of dfu_trigger_reset()
After the commit 1cc03c5c53 ("dfu: Provide means to find difference between
dfu-util -e and -R") the dangling ptototype appeared. Remove it here.

Fixes: 1cc03c5c53 ("dfu: Provide means to find difference between dfu-util -e and -R")
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2020-01-07 14:37:50 +01:00
Christian Hewitt
b9d5480fdb ARM: dts: Import Khadas VIM3L DT from Linux 5.5-rc1
Import the Khadas VIM3L device-tree from [1]

[1] e42617b825f8 ("Linux 5.5-rc1")

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-01-07 11:16:53 +01:00
Simon Glass
b9dea62b6b video: meson: Drop unnecessary header includes
These files should not be included in meson header files. Drop them and
tidy up the affected C files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-01-07 11:15:24 +01:00
Rasmus Villemoes
b6e7ef4bf7 ARM: mxs: spl_boot.c: make early_delay more robust
It's true that booting normally doesn't take long enough for the
register to roll (which actually happens in a little over an hour, not
just a few seconds). However, the counter starts at power-on, and if
the board is held in reset to be booted over USB, one actually risks
hitting wrap-around during boot, which can both result in too short
delays (if the "st += delay" calculation makes st small) and
theoretically also unbound delays (if st ends up being UINT_MAX and
one just misses sampling digctl_microseconds at that point).

It doesn't take more code to DTRT, and once bitten, twice shy.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-01-07 10:26:57 +01:00
Michael Trimarchi
b1278a8e3e ARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methods
Engicam i.CoreM6 1.5 Quad/Dual MIPI dtsi is reusing fec node
from Engicam i.CoreM6 dtsi but have sampe copy of phy-reset-gpio
and phy-mode properties.

So, drop this phy reset methods from imx6qdl-icore-1.5 dsti file.

Cc: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-07 10:26:57 +01:00
Jagan Teki
f838ebfe5a ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL
The EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation is based on
the 1.5 version of the i.Core MX6 cpu module. The 1.5 version
differs from the original one for a few details, including the
ethernet PHY interface clock provider.

With this commit, the ethernet interface works properly:
SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver

While before using the 1.5 version, ethernet failed to startup
do to un-clocked PHY interface:
fec 2188000.ethernet eth0: could not attach to PHY

Similar fix has merged for i.Core MX6Q but missed to update for DL.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-07 10:26:57 +01:00
Jagan Teki
d159b0236b ARM: dts: icorem6: Sync engicam device trees from v5.4
Sync Engicam device tree file from v5.4 linux-next.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-07 10:26:57 +01:00
Michael Trimarchi
57de577950 configs: imx6-engicam: Drop fec phy address and mode
Now all the fec related phy properties are now accessible
via dts. So drop the explicit config items from common
config file, imx6-engicam.h

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-07 10:26:57 +01:00
Michael Trimarchi
90d466593f board: engicam: Fix the ethernet clock initialization
According to the SOM and reference board the clock
can be taken from the external pin or provided from
ENET_REF_CLK. Add a new function that make the proper
set according the board type.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-07 10:26:57 +01:00
Michael Trimarchi
8811c4d046 board: engicam: Cleanup fdt file and board mapping
Make easy to map fdt file to board in order to use
this information later to apply specific change to
specific board combination.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-07 10:26:57 +01:00
Rasmus Villemoes
abaf5c9804 arm: mxs: be more careful when enabling gpmi_clk
The data sheet says that the DIV field cannot change while the CLKGATE
bit is set or modified. So do it a little more carefully, by first
clearing the bit, waiting for that to appear, then setting the DIV
field.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-01-07 10:26:57 +01:00
Rasmus Villemoes
fb94625229 arm: mxs: fix comments in arch_cpu_init to match the code
The comment says to clear the bypass bit, but in fact it sets it, thus
selecting ref_xtal. And the next line of code does not set the divider
to 12, but to (the reset value of) 1.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-01-07 10:26:57 +01:00
Rasmus Villemoes
bb09bd5f69 arm: mxs: fix register definitions for clkctrl_gpmi and clkctrl_sspX
I tried clearing a bit by writing to hw_clkctrl_gpmi_clr, then
busy-waiting for it to actually clear. My board hung. The data sheet
agrees, these registers do not have _set, _clr, _tog, so fix up the
definitions. git grep -E 'clkctrl_(gpmi|ssp[0-9])_' says that nobody
uses those non-existing ops registers.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-01-07 10:26:57 +01:00
Fabio Estevam
32efcbc09f imx8mm_evk: Adjust the environment for booting a mainline kernel
Adjust the environment for booting a mainline kernel by default.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-07 10:26:57 +01:00
Igor Opaniuk
061b63b775 mach-imx: nandbcb: improve cmd help
Add info about supported i.MX7, improve details the usage of
bcbonly subcommand.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07 10:26:57 +01:00
Fabio Estevam
08b72863d7 mx6slevk: Fix the pmic_get() parameter in the DM case
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.

Reported-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-07 10:26:57 +01:00
Fabio Estevam
94b293636f mx6sllevk: Fix the pmic_get() parameter in the DM case
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.

Reported-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-07 10:26:57 +01:00
Fabio Estevam
cb14a5bf66 mx7dsabresd: Fix the pmic_get() parameter in the DM case
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.

Reported-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-07 10:26:57 +01:00
Frieder Schrempf
83083febf5 ddr: imx8m: Return error values from LPDDR4 training
In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.

Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2020-01-07 10:26:57 +01:00
Frieder Schrempf
162c72c804 tools: imx8m_image: Change source path for DDR firmware to build dir
The DDR firmware binaries are not part of the U-Boot source code, so
we should look for them in the build directory, where they need to be
copied to before building U-Boot.

The ATF binary is already fetched from the build directory, but the
README files for the i.MX8M EVKs claim that it needs to be copied to
the source directory (which is still true for in-tree builds, but not
in general). Therefore we also fix the READMEs to use the build
directory as the correct location for all additional binary files.

Sined-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2020-01-07 10:26:57 +01:00
Tom Rini
44ad496143 arm: imx: Default to SYS_THUMB_BUILD for i.MX6/7
In the case of i.MX6 and i.MX7 family SoCs it is safe (from an errata
point of view) to use thumb2 by default to save space.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-01-07 10:26:57 +01:00
Igor Opaniuk
c0f037f6a2 mach-imx: bootaux: elf firmware support
Currently imx-specific bootaux command doesn't support ELF format
firmware for Cortex-M4 core.

This patches introduces a PoC implementation of handling elf firmware
(load_elf_image_phdr() was copy-pasted from elf.c just for PoC).
ELF64 binaries isn't supported yet.

This has the advantage that the user does not need to know to which
address the binary has been linked to. However, in order to handle
and load the elf sections to the right address, we need to translate the
Cortex-M4 core memory addresses to primary/host CPU memory
addresses (Cortex A7/A9 cores).

This allows to boot firmwares from any location with just using
bootaux, e.g.:
> tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr}

Similar translation table can be found in the Linux remoteproc
driver [1].

[1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07 10:26:56 +01:00
Igor Opaniuk
ebabbf1169 colibri_imx7: migrate to DM_ETH
Migrate to DM_ETH and remove hardcoded pinmux configuration.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07 10:26:56 +01:00
Igor Opaniuk
45997eb6c0 ARM: dts: imx7: imx7_colibri: introduce fec node
Sync DTS with the mainline Linux and introduce fec node and
regulator configuration for rn5t567 PMU.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07 10:26:56 +01:00
Igor Opaniuk
a781ed271e apalis_imx6: migrate to DM_ETH
Migrate to DM_ETH and remove hardcoded pinmux configuration.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07 10:26:56 +01:00
Igor Opaniuk
f9be62a608 ARM: dts: imx6_apalis: introduce fec node
Sync DTS with the mainline Linux and introduce fec node.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07 10:26:56 +01:00