The RD-AC5X doesn't make use of EFI or SMBIOS. Recently we started seeing
boot failures such as
WARNING: SMBIOS table_address overflow 27f60f020
Failed to write SMBIOS table
initcall failed at event 10/(unknown) (err=-22)
### ERROR ### Please RESET the board ###
The error is because the physical address of the RAM on the AC5X SoC is
above the 32GiB boundary. As we don't need SMBIOS or EFI this can be
safely disabled.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This reverts commit 5c1c6b7306. The reason
for switching to i2c-gpio was due to an issue we were seeing in the
Linux kernel where the CPU would lock up on certain adverse I2C bus
conditions. We were never able to reproduce the lockup in U-Boot but
assumed that was probably just luck.
Since then we have discovered that the lock up was due to the I2C
transaction offload engine in the I2C controller not coping with the
adverse bus conditions (basically it thinks there's another master and
waits for a STOP condition that never comes). U-Boot doesn't use the I2C
offload feature so is not susceptible to the lockup.
We can therefore safely return to using the built-in I2C controller.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The x240 doesn't make use of EFI or SMBIOS. Recently we started seeing
boot failures such as
WARNING: SMBIOS table_address overflow 23f60c020
Failed to write SMBIOS table
initcall failed at event 10/(unknown) (err=-22)
### ERROR ### Please RESET the board ###
The error is because the physical address of the RAM on the AC5X SoC is
above the 32GiB boundary. As we don't need SMBIOS or EFI this can be
safely disabled.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add EEPROM detection initialisation for phyCORE-i.MX8MM and
print SoM information during boot when successful.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
Tested-by: Yannic Moog <y.moog@phytec.de>
ZyXEL NSA325 specifications:
Marvell Kirkwood 88F6282 SoC
1.6 GHz CPU
1x GBE LAN port (Marvell MV88E1318)
512 MB RAM
128 MB Eon NAND, SLC
I2C
1x USB 3.0 (on PCIe bus)
2x USB 2.0
2x SATA (hot swap slots)
Serial console
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
When using a list of writeable variables, the initial values come
from the built-in default environment since commit 5ab8105836 ("env:
Complete generic support for writable list").
Remove unnecessary misuse of CONFIG_ENV_IS_NOWHERE as default environment.
Based on the fix done by commit b16fd7f75f ("imx6q: acc: Remove misuse
of env is nowhere driver").
Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Use DM_I2C and DM_SERIAL as it is now mandatory.
Signed-off-by: Andrej Rosano <andrej.rosano@withsecure.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Enable USB SDP SPL aka serial downloader recovery mode support.
While at it also enable fastboot support which may be used to
subsequently load further stages like a Toradex Easy Installer FIT
image.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The Gateworks imx8mm-venice-gw7905-0x consists of a SOM + baseboard.
The GW700x SOM contains the following:
- i.MX8M Mini SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- RGMII PHY
- PMIC
- SOM connector providing:
- FEC GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 2.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW7905 Baseboard contains the following:
- GPS
- microSD
- off-board I/O connector with I2C, SPI, GPIO
- EERPOM
- PCIe clock generator
- 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
- 1x half-length miniPCIe socket with USB2.0 and USB3.0
- USB 3.0 HUB
- USB Type-C with USB PD Sink capability and peripheral support
- USB Type-C with USB 3.0 host support
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks imx8mp-venice-gw73xx-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW73xx Baseboard contains the following:
- 1x RJ45 GbE (eQoS from SOM)
- 1x RJ45 GbE (PCI)
- off-board I/O connector with MIPI-CSI (3-lane), MIPI-DSI (4-lane),
- off-board I/O connector with RS232/RS485
- off-board I/O connector with SPI
- off-board I/O connector with I2C, UART, and GPIO
I2C, I2S and GPIO
- microSD (1.8V/3.3V)
- GPS
- Accelerometer
- EERPOM
- USB 3.0 Hub
- Front Panel bi-color LED
- re-chargeable battery (for RTC)
- PCIe clock generator
- PCIe switch
- on-board 802.11abgnac 1x1 WiFi and Bluetooth 5.2
- 1x USB Type-A host socket with USB 3.0 support
- 1x USB OTG with USB 2.0 support
- 2x MiniPCIe socket with PCI and USB 2.0
- 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0
- Wide range DC input supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks imx8mp-venice-gw72xx-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW72xx Baseboard contains the following:
- 1x RJ45 GbE (eQoS from SOM)
- 1x RJ45 GbE (PCI)
- off-board I/O connector with MIPI-CSI (3-lane), MIPI-DSI (4-lane),
- off-board I/O connector with RS232/RS485
- off-board I/O connector with SPI
- off-board I/O connector with I2C, UART, and GPIO
I2C, I2S and GPIO
- microSD (1.8V/3.3V)
- GPS
- Accelerometer
- EERPOM
- USB 3.0 Hub
- Front Panel bi-color LED
- re-chargeable battery (for RTC)
- PCIe clock generator
- PCIe switch
- 1x USB Type-A host socket with USB 3.0 support
- 1x USB OTG with USB 2.0 support
- 1x MiniPCIe socket with PCI and USB 2.0
- 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0
- Wide range DC input supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
clk:
- remove additional compatible strings for Versal NET
net:
- zynq_gem: Fix clock calculation for MDC for higher frequencies
pinctrl:
- core: Extend pinmux status buffere size
- zynqmp driver: Show also tristate configuration
test:
- add test case for pxe get
Xilinx:
- describe SelectMAP boot mode
Zynq:
- Fix nand description in DT
ZynqMP:
- DTS sync patches with kernel and also W=1 related fixes
- Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c
description for other SC based boards
- k24 psu_init cleanup
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZSjvwAAKCRDKSWXLKUoM
IR34AJ92oum3pJXKxKREEZh0dCfDvJlE/wCggyzxI2T5liJfRG5jzlUuDjiLLU0=
=u1bz
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2024.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.01-rc1 v3
clk:
- remove additional compatible strings for Versal NET
net:
- zynq_gem: Fix clock calculation for MDC for higher frequencies
pinctrl:
- core: Extend pinmux status buffere size
- zynqmp driver: Show also tristate configuration
test:
- add test case for pxe get
Xilinx:
- describe SelectMAP boot mode
Zynq:
- Fix nand description in DT
ZynqMP:
- DTS sync patches with kernel and also W=1 related fixes
- Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c
description for other SC based boards
- k24 psu_init cleanup
The malloc capacity in DRAM at R5 SPL is set to 1MB which isn't
sufficient to load the new tispl.bin to
enable loading of tispl.bin the size is increased by 256KB to 1.25MB.
Cc: Nikhil M Jain <n-jain1@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
Switch to using bootstd. Note with this change, we will stop using
distro_bootcmd and instead depend entirely on bootflow method of
starting the system up.
Drop header files that are no longer needed in am64x_evm.h.
k3_dfu.h is available via k3_dfu.env in am64x.env.
Drop unused macro CFG_SYS_SDRAM_BASE1.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Currently we have all drivers for use USB stack on A1-series
SoC's. Let's enable USB options for the Amlogic AD401 reference A1
SoC board.
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231005085434.74755-9-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
All K3 boards now are secure by default, instead of setting this in each
defconfig, make it implied by the ARCH config.
The only exception is IOT2050, which I do not believe will have any
problems with being a TI_SECURE_DEVICE, but for now turn it off to keep
its config the same.
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Added new xenguest_arm64_virtio_defconfig which
enables support for virtio-blk using various types
of transport like virtio-pci, vrtio-mmio. Currently
supported: up to 2 PCI host bridges and 10 MMIO devices.
Note: DT parsing code was partly taken from pci-uclass.c
Limitation: All memory regions should be
below 4GB address space.
Signed-off-by: Andrii Chepurnyi <andrii_chepurnyi@epam.com>
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. This makes
the defconfigs that make use of PPA obsolete, so remove them.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
[Merged part 1 and part 2]
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Allow for a proper configuration of CFI flash banks avaialble on the vexpress_ca9x4
board. Without this option, the CFI flash incorrectly detects that the board has two
banks of 32MB flash devices, while in reality, the board provides
two flash banks, each with 64MB size. As a result, it becomes impossible to e.g. to
save u-boot env in flash. According to device tree for this board and
its implementation in QEMU, the CFI width should be set to 32 bits.
After applying this fix, CFI flash will correctly detect both flash
banks each with a size of 64MB. As as result the functionality of e.g. saving u-boot
env will work correctly.
Tested on QEMU 6.2.0.
Cc: Kristian Amlie <kristian.amlie@northern.tech>
Signed-off-by: Patryk Biel <pbiel7@gmail.com>
Reviewed-by: Kristian Amlie <kristian.amlie@northern.tech>
- Add Board: rk3568 Bananapi R2Pro;
- Update pcie bifurcation support;
- dwc_eth_qos controller support for rk3568 and rk3588;
- Compressed binary support for U-Boot on rockchip platform;
- dts and config updates for different board and soc;
[ trini: Fix conflict on include/spl.h ]
Signed-off-by: Tom Rini <trini@konsulko.com>
With PMIC_RK8XX, SYSRESET and CMD_POWEROFF options enabled it is
possible to power down a board using the poweroff command and turn the
board back on using a power button.
Enable the poweroff command on RK356x boards that have a button wired
to PMIC pwron.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
all rk3308 boards should use their own dtb file.
also, change fdt_addr_r to avoid following error:
"ERROR: Did not find a cmdline Flattened Device Tree"
it happens on Radxa ROCK Pi S (256MB/512MB) with kernel built from
Radxa BSP.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Without DOS_PARTITION support U-Boot is not able to boot an OS stored
into an SD card with MBR partitions table. This is still a quite common
case so add DOS_PARTITION (only for U-Boot proper build) to Rockchip
RK3308 EVB, Radxa ROCK Pi S and Firefly roc-rk3308-cc boards: they are
the only RK boards missing of DOS_PARTITION.
Reported-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Bananapi R2 Pro board.
tested:
- sdcard
- both front usb-ports
- sata
- wan-port
lan-ports are connected to mt7531 switch where driver needs to be
separated from mtk ethernet-driver.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Enable DWC_ETH_QOS_ROCKCHIP and related PHY driver on RK3588 boards that
have an enabled gmac node and drop ETH_DESIGNWARE and GMAC_ROCKCHIP for
remaining RK3588 boards.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable DWC_ETH_QOS_ROCKCHIP and related PHY driver on RK356x boards that
have an enabled gmac node.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a minimal generic RK3566/RK3568 board that only have eMMC and SDMMC
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3566/RK3568 boards that follow reference board design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable missing PCIe Kconfig options now that PCIe bifurcation is fixed
to make use of the two on-board RTL8125B and the M.2 slot on NanoPi R5C
and NanoPi R5S.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update and sync Kconfig options for NanoPi R5C and NanoPi R5S with other
RK3568 boards.
SPL_FIT_SIGNATURE is enabled to add a checksum validation of the FIT
payload, also add LEGACY_IMAGE_FORMAT to keep boot scripts working.
OF_SPL_REMOVE_PROPS, SPL_DM_SEQ_ALIAS and SPL_PINCTRL change ensure
pinctrl for eMMC, SD-card and UART2 is applied in SPL.
MMC_HS200_SUPPORT and SPL counterpart is enabled to speed up eMMC load
times from on-board eMMC 5.1 modules.
Drop remaining unused or unsupported options to sync with other RK3568
boards.
Also sync device tree from linux v6.4 and drop u-boot,spl-boot-order and
use the default from rk356x-u-boot.dtsi.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rename this so that SPL is first, as per U-Boot convention. Also add
PAYLOAD_ since this is where in memory the parameters for the payload
have been stored.
Signed-off-by: Simon Glass <sjg@chromium.org>
We like to put the SPL first so it is clear that it relates to SPL. Rename
various malloc-related options which have crept in, to stick to this
convention.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
+ ae350: modify memory layout and target name
+ ae350: use generic RISC-V timer driver in S-mode
+ Support bootstage report for RISC-V
+ Support C extension exception command for RISC-V
+ Add Starfive timer support
Kernel commit d93036b47f35 ("arm64: dts: ti: k3-j721e-mcu_wakeup: Add
HyperBus node") was merged to kernel without its dependent patch [1].
Similar fix is needed in U-Boot, and hbmc currently breaks boot. Till
this gets fixed in U-Boot, disable the config by default so that the
hbmc probe that happens in board/ti/j721e/evm.c will not take place
and lead to boot failure.
[1] https://lore.kernel.org/all/20230424184810.29453-1-afd@ti.com/
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
_ alignment with kernel DT v6.5 for stm32f429 and stm32f746
_ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco
STM32 MPU:
_ alignment with kernel DT v6.6-rc1
_ add RNG support for stm32mp13
_ add USB, USB boot and stm32prog command support for stm32mp13
_ add support of USART1 clock for stm32mp1
_ only print RAM and board code with SPL_DISPLAY_PRINT flag for
stm32mp1
_ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc
for stm32mp15xx DHCOR
-----BEGIN PGP SIGNATURE-----
iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmUdaJccHHBhdHJpY2Uu
Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/ptHxEACdibF5EoRb40qhQCWB
mwW50s76xWOyHGOGjSe3l18zxPdBjQ+9rnT8/A+mjaa8he4kMX9EZJyYRogcz7eR
QcnSeu9Q4L8bKbqnPBOpKF6TN7rFOIUcu+BWp3o8jZ+7/q7OSJrVLsjbXtCuCLnB
q5Pie/in7hmHJsQr6LJ4r31chW6Zm4VDuFiXquuxyE/c94Q8Ue27ag1/RfXL8b/g
Ir9aO+PAldGnVdnhPz4e6PZhzMfCVafw+DR7GVx3Zfnx2bg/dajo38UaLBDdEIS1
EIKONU2CBT/W1kPkLFiz+NdaYCzK9EL+RIbN/iG7ms+ds1+wc3zXpWwqZFASfIod
ZF788Up+wW+3SrKI2ySFjhQroNzDascn+bbHm4yJuAsORqY0XkxjSuWcSz++q8Hs
eMTw/R4uMfEiDvN1A7xlhBMuBrBHk4/6bdCRx2R6nkWes542fsgjXy8tGRWyUgnY
nbpTfYU07N8ck6arZ36KThedD7whJHHRcBYtLjhRG+lKbD0epWy67pXgTr9edTLf
U6ddH+Tndn4qhx067VhZ8vEXTCzypt4lY61MLcM0b9z8S1nJDn8b8jmiii7IR76L
/ocXzuLvNWHfmwNnB2hj/YY+n78vlZhegUxL5/6sH9lNebnewyEzCkVENNELUSYf
8M6vEZprvuhN44Z6hBUWZxXk0w==
=1mUx
-----END PGP SIGNATURE-----
Merge tag 'u-boot-stm32-20231004' of https://source.denx.de/u-boot/custodians/u-boot-stm
STM32 MCU:
_ alignment with kernel DT v6.5 for stm32f429 and stm32f746
_ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco
STM32 MPU:
_ alignment with kernel DT v6.6-rc1
_ add RNG support for stm32mp13
_ add USB, USB boot and stm32prog command support for stm32mp13
_ add support of USART1 clock for stm32mp1
_ only print RAM and board code with SPL_DISPLAY_PRINT flag for
stm32mp1
_ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc
for stm32mp15xx DHCOR
[ Fix merge conflict at board/st/common/stm32mp_dfu.c ]
Signed-off-by: Tom Rini <trini@konsulko.com>
Activate the command stm32prog with CONFIG_CMD_STM32MPROG.
The CONFIG_SET_DFU_ALT_INFO is also activated to support
the required weak functions for the DFU virtual backen defined in
board/st/common/stm32mp_dfu.c.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Default embed this configuration. If OP-TEE PTA RNG is exposed, it means
that the RNG is managed by the secure world. Therefore, the RNG node
should be disabled in the device tree as an access would be denied
by the hardware firewall.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
