Commit graph

4660 commits

Author SHA1 Message Date
Anton Vorontsov
d892b2dbb4 mpc83xx: MPC8360E-RDK: rework ddr setup, enable ecc
Current DDR setup easily causes memory corruption, this patch fixes it.

Also fix TIMING_CFG0_MRS_CYC definition.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:47 -05:00
Anton Vorontsov
d47d49cc37 mpc83xx: MPC8360E-RDK: configure pario pins for AD7843 and FHCI
This patch adds qe pario pins configuration for AD7843 ADC/Touchscreen
controller and FHCI (QE USB).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:47 -05:00
Anton Vorontsov
7ad9594909 mpc83xx: MPC8360E-RDK: add support for NAND
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:46 -05:00
Anton Vorontsov
9a3e832aeb mpc83xx: MPC8360E-RDK: use RGMII_RXID interface mode
This is needed for BCM PHYs to work on this board.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:46 -05:00
Anton Vorontsov
300615dc5d uec: add support for Broadcom BCM5481 Gigabit PHY
This patch adds basic support for Broadcom BCM5481 PHY.

RXD-RXC delay quirk comes from MPC8360E-RDK BSP source, author is
Peter Barada <peterb@logicpd.com>.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:46 -05:00
Anton Vorontsov
6a600c3a18 uec: add support for RGMII_RXID interface mode
PHY drivers will use it to setup software delay between RXD and RXC
signals.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:46 -05:00
Anton Vorontsov
91cdaa3a9d uec: add support for gbit mii status readings
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:45 -05:00
Anton Vorontsov
aabce7fb50 83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boards
This is primarily for the early console support.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:45 -05:00
Anton Vorontsov
2bd7460e92 83xx: initialize serdes for MPC837XRDB boards
On the MPC8377ERDB: 2 SATA and 2 PCI-E.
On the MPC8378ERDB: 2 PCI-E
On the MPC8379ERDB: 4 SATA

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:45 -05:00
Anton Vorontsov
453316a2a1 83xx: serdes setup routines
This patch adds few routines to configure serdes on 837x targets.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:45 -05:00
Anton Vorontsov
a796cdf9c3 83xx: split COBJS onto separate lines
..plus get rid of some #ifdefs in the .c files.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:44 -05:00
Anton Vorontsov
46a3aeea73 83xx: nand support for MPC837XRDB boards
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:44 -05:00
Jerry Van Baren
82e45a2041 Enable CONFIG_FLASH_SHOW_PROGRESS on the MPC8360EMDS.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:44 -05:00
Michael Barkowski
0fa7a1b471 mpc8323erdb: remove RTC and add EEPROM
There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM.

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:44 -05:00
Michael Barkowski
5bbeea86eb mpc8323erdb: Improve the system performance
The following changes are based on kernel UCC ethernet performance:

1.  Make the CSB bus pipeline depth as 4, and enable the repeat mode
2.  Optimize transactions between QE and CSB.  Added CFG_SPCR_OPT
    switch to enable this setting.

The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:

3.  CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4.  CS0_CONFIG[ODT_WR_CONFIG] set to 1.  Was a reserved setting
    previously.
5.  TIMING_CFG_1[WRREC] is changed from 3clks to 2clks  (based on
    Twr=15ns, and this was already the setting in DDR_MODE)
6.  TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
    Trp=15ns)
7.  TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
    Tras=40ns)
8.  TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
    Trcd=15ns)
9.  TIMING_CFG_1[REFREC] changed from 21 clks to 11clks.  (based on
    Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks.  (based
    on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
    on CL=3 and WL=2).

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:44 -05:00
Michael Barkowski
fc549c871f mpc8323erdb: use readable DDR config macros
Use available shift/mask macros to define DDR configuration.

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:43 -05:00
Timur Tabi
89c7784ed9 83xx: Add Vitesse VSC7385 firmware uploading
Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
the Vitesse VSC7385 firmware.  Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
Cleaned up the board header files to make selecting the VSC7385 easier to
control.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:43 -05:00
Timur Tabi
b55d98c6d5 NET: Add Vitesse VSC7385 firmware uploading
The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX
and other boards.  A small firwmare must be uploaded to its on-board memory
before it can be enabled.  This patch adds the code which uploads firmware
(but not the firmware itself).

Previously, this feature was provided by a U-Boot application that was
made available only on Freescale BSPs.  The VSC7385 firmware must still
be obtained separately, but at least there is no longer a need for a separate
application.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
2008-03-25 19:16:43 -05:00
Wolfgang Denk
aa6f6d171a Coding Style cleanyp; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-26 00:52:10 +01:00
Wolfgang Denk
6525489323 Merge branch 'master' of git://www.denx.de/git/u-boot-mips 2008-03-26 00:44:52 +01:00
Wolfgang Denk
08e9443230 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xx 2008-03-26 00:44:32 +01:00
Jerry Van Baren
43ddd9c820 Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_T
These defines embedded the u-boot env variables and/or the bd_t structure
in the fdt blob.  The conclusion of discussion on the u-boot email list
was that embedding these in the fdt blob is not useful: there are better
ways of passing the data (in fact, the fdt blob itself replaces the
bd_t struct).

The only board that enables these is the stxxtc and they don't appear
to be used by linux.

Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-26 00:22:39 +01:00
Stefan Roese
22ed228574 rtc: Remove 2nd reference to max6900.o in drivers/rtc/Makefile
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-26 00:06:19 +01:00
Kyungmin Park
1bb707c39a Add Flex-OneNAND booting support
Flex-OneNAND is a monolithic integrated circuit with a NAND Flash array
using a NOR Flash interface. This on-chip integration enables system designers
to reduce external system logic and use high-density NAND Flash
in applications that would otherwise have to use more NOR components.

Flex-OneNAND enables users to configure to partition it into SLC and MLC areas
in more flexible way. While MLC area of Flex-OneNAND can be used to store data
that require low reliability and high density, SLC area of Flex-OneNAND
to store data that need high reliability and high performance. Flex-OneNAND
can let users take advantage of storing these two different types of data
into one chip, which is making Flex-OneNAND more cost- and space-effective.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2008-03-26 00:05:32 +01:00
André Schwarz
c512389cc4 MPC5200: support setup without FEC
Include FEC specific nodes in ft_cpu_setup only if CONFIG_MPC5xxx_FEC is
defined. Systems without FEC, i.e. no FEC node in DTB, should be possible.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
2008-03-25 23:59:43 +01:00
Jon Loeliger
aa3511e422 FSL: Move board/mpc8266ads under board/freescale
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-03-25 23:00:40 +01:00
Jon Loeliger
7f1d846e5c FSL: Move board/mpc7448hpc2 under board/freescale
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-03-25 23:00:36 +01:00
Jon Loeliger
b7e24d283e FSL: Move board/mpc8260ads under board/freescale
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-03-25 23:00:00 +01:00
goda.yusuke
6a8a5dc475 net: Add support AX88796L ethernet device
AX88796L is device of NE2000 compatible.
This patch support AX88796L ethernet device.

Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-25 22:55:15 +01:00
Wolfgang Denk
e0a6140dd3 ne2000 driver: change #ifdef to Makefile conditional compilation
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-25 22:50:41 +01:00
goda.yusuke
e710185aae net: Divided code of NE2000 ethernet driver
There are more devices of the NE2000 base.
A present code is difficult for us to support more devices.
To support more NE2000 clone devices, separated the function.

Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-25 22:48:58 +01:00
Mike Frysinger
395bce4f59 net/Blackfin: move on-chip MAC driver into drivers/net/
The Blackfin on-chip MAC driver was being managed in the BF537-STAMP board
directory, but it is not board specific, so relocate it to the drivers dir
so that other Blackfin ports can utilize it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-03-25 22:35:26 +01:00
Mike Frysinger
8a30b47009 smc91111: use SSYNC() rather than asm(ssync) for Blackfin
Since the "ssync" instruction may have hardware anomalies associated with
it, have the smc91111 driver use the SSYNC macro rather than invoking it
directly.  We workaround all the anomalies via this macro.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-03-25 22:32:25 +01:00
Bryan O'Donoghue
77ff7b7444 8xx: Update OF support on 8xx
This patch does some shifting around of OF support on 8xx.

Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie>
2008-03-25 22:28:34 +01:00
Kumar Gala
9c666a7db0 ppc: Allow boards to specify how much memory they can map
For historical reasons we limited the stack to 256M because some boards
could only map that much via BATS.  However newer boards are capable of
mapping more memory (for example 85xx is capble of doing up to 2G).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-25 22:26:11 +01:00
Bryan O'Donoghue
a6f5f317cd 8xx : Add OF support to Adder875 board port - resubmit
Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie>
2008-03-25 22:20:36 +01:00
Kumar Gala
d058698fd2 Add setexpr command
Add a simple expr style command that will set an env variable as the result
of the command.  This allows us to do simple math in shell.  The following
operations are supported: &, |, ^, +, -, *, /.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-25 22:16:15 +01:00
Jon Loeliger
3f105faa64 FSL: Move board/mpc7448hpc2 under board/freescale
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-03-25 09:51:43 -05:00
Jon Loeliger
449c703374 FSL: Move board/mpc8266ads under board/freescale
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-03-25 09:51:43 -05:00
Jon Loeliger
5863577989 FSL: Move board/mpc8260ads under board/freescale
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-03-25 09:51:43 -05:00
Shinya Kuribayashi
8a77398395 [MIPS] Move gth2_config from ARM section to MIPS
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:08 +09:00
Shinya Kuribayashi
373b16fc0c [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
d98e348e2e [MIPS] Fix dcache_status()
You can't judge UNCACHED by Config.K0 LSB.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
b0c66af53e [MIPS] Introduce _machine_restart
Handles machine specific functions by using weak functions.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
decaba6f5c [MIPS] Cleanup CP0 Status initialization
Add setup_c0_status from Linux. For the moment we disable interrupts, set
CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for
reset-time configuration and will work well across most processors.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
d43d43ef28 [MIPS] Initialize CP0 Cause before setting up CP0 Status register
Without this change, we'll be suffering from deffered WATCH exception
once Status.EXL is cleared. Make sure Cause.WP is cleared.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
2613862323 [MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init()
Move things to appropriate place.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
ccf8f824ef [MIPS] Implement flush_cache()
We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you
don't need to do Hit_Invalidate_I, but flush_cache() needs it since this
function is used not only in U-Boot specfic programs but also at loading
target binaries.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:06 +09:00
Shinya Kuribayashi
2e0e5271aa [MIPS] Fix I-/D-cache initialization loops
Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I
again per a loop for I-cache initialization. But according to 'See MIPS
Run', we're encouraged to use three separate loops rather than combining
them *for both I- and D-cache*. This patch tries to fix this.

In accordance with fixing above, mips_init_[id]cache are separated from
mips_cache_reset(), and rewrite cache loops are completely rewritten with
useful macros.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:06 +09:00
Shinya Kuribayashi
1898840797 [MIPS] Replace memory clearance code with f_fill64
This routine fills memory with zero by 64 bytes, and is 64-bit capable.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:06 +09:00