Commit graph

25 commits

Author SHA1 Message Date
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Simon Glass
da409ccc4a dm: core: Replace of_offset with accessor (part 2)
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:04 -06:00
Bin Meng
770ee01742 x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode
Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).

Prior to this fix the blue USB port on the Minnowboard Max was
unusable since USB_HOST_EN0 was set high then immediately set
low when USB_HOST_EN1 was written.

This also resolves the 'gpio clear | set' command warning like:
  "Warning: value of pin is still 0"

Signed-off-by: George McCollister <george.mccollister@gmail.com>
<rebased on latest origin/master, fixed all baytrail boards>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-17 17:13:06 +08:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Bin Meng
d8906c1f3f x86: Probe pinctrl driver in cpu_init_r()
At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:

 - Pin's PADs only gets configured when GPIO driver is probed, which
   is not done by default. This leaves the board in a partially
   functional state as we must initialize PADs correctly to get
   perepherals fully working.
 - The probe routine of pinctrl driver is called multiple times, as
   normally there are multiple GPIO controllers. It should really
   be called just once.

Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
2016-06-12 12:19:35 +08:00
Bin Meng
8142340ee3 x86: ich6_gpio: Output return value of syscon_get_by_driver_data()
The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12 12:19:35 +08:00
Simon Glass
779653b0cb x86: Drop all the old pin configuration code
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
15cf75ec15 x86: gpio: Allow the pinctrl driver to set up the pin config
Rather than setting up the pin configuration in the GPIO driver, use the
new pinctrl driver to do it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
d6d50db8a3 x86: gpio: Correct GPIO setup ordering
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.

Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Bin Meng
3ddc1c7bd3 x86: ich6_gpio: Convert to use proper DM API
At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.

Update the device tree files to show the GPIO controller within the PCH,
so that PCI access works as expected. This also adds '#address-cells'
and '#size-cells' to the PCH node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Simon Glass
df1c9eb505 x86: gpio: Tidy up gpio_ich6_get_base() and callers
This function can return an error. Correct the detection of this error so
that it works even with large 32-bit addresses.

The return value is set up for returning an I/O address but the function is
also used to return a memory-mapped address. Adjust the return code to make
this work.

Also add a bit more debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:15 -07:00
Simon Glass
e7cc0b6f00 x86: gpio: Correct calls to _ich6_gpio_set_direction()
These calls seem to be incorrect. The function expects an I/O address but
the existing callers pass the value at an I/O address. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:15 -07:00
Simon Glass
8b097916fa x86: Add some missing global_data declarations in files that use gd
Some files use global_data but don't declare it. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Gabriel Huau
5318f18d2c x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:32:08 -06:00
Simon Glass
e564f054af dm: core: Add dev_get_uclass_priv() to access uclass private data
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:42 -06:00
Simon Glass
31f57c2873 x86: Add a x86_ prefix to the x86-specific PCI functions
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.

In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-16 19:27:41 -06:00
Bin Meng
b71eec3129 x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
2795573a8c x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Axel Lin
0a54745fc2 gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()
Current code does not set gpio output value in ich6_gpio_direction_output(),
fix it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Simon Glass
1b4f25ff8e x86: ivybridge: Add support for early GPIO init
When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.

In this implementation, board files should call ich_gpio_set_gpio_map()
before the GPIO driver is used in order to provide the GPIO information.
We use the early PCI interface so that this driver can now be used before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
7414112d70 dm: x86: Convert Intel ICH6 GPIO driver to use driver model
Convert over this driver, using device tree to pass in the required
information. The peripheral is still probed, just the number of GPIO banks
and their offsets is in the device tree (previously this was a table in
the driver).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:28 -06:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Bill Richardson
57be9172fc x86: gpio: Add additional GPIO banks to the ICH6 driver
We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the
same place across all versions. This change adds two more banks, for up to
96 GPIOS.

BUT:
- Not all chipsets have the same number of GPIOs
- Not all chipsets have the same number of GPIO banks
- Not all chipsets put the additional banks at the same offset from GPIOBASE
- There so many chipset variants that it's pretty much impossible to support
  them all, or even keep track of the new ones.

So, although this adds suppport for the additional banks that seem to work
for the particular variants of CougarPoint Mobile chipsets that we've tried,
there's no chance it will support everything Intel produces. Good luck.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Bill Richardson
55ae10f8db x86: gpio: Add GPIO driver for Intel ICH6 and later.
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00