Commit graph

2434 commits

Author SHA1 Message Date
Prafulla Wadaskar
bfb6d510e9 Kirkwood: Makefile cleanup- fixed ordering (cosmetic change)
As per coding guidlines, it is good to maintain proper ordering
in the makefiles.
This was missed during initial coding, corrected here.

This was discovered during orion5x code review
Thanks to Albert Aribaud for this.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2010-01-23 08:15:48 -06:00
Minkyu Kang
d8e5f55475 s5pc1xx: update cache routines
Because of v7_flush_dcache_all is moved to omap3/cache.S
and s5pc110 needs cache routines, update s5pc1xx cache routines.

l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S
and invalidate_dcache is modified for SoC specific.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2010-01-23 08:15:48 -06:00
Detlev Zundel
57ae8a5cce mpc512x: Use in/out accessors for all registers
This is not only a cosmetic change as it fixes the real bug of board
reset not working with the ELDK 4.2 toolchain.

Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-21 23:00:45 +01:00
Wolfgang Denk
4ac63017c3 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-01-21 22:27:54 +01:00
Felix Radensky
33c8c66423 ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs
On platforms where SPD EEPROM and another EEPROM have adjacent
I2C addresses SPD_EEPROM_ADDRESS should be defined as a single
element array, otherwise DDR2 setup code would fail with the
following error:

ERROR: Unknown DIMM detected in slot 1

However, fixing SPD_EEPROM_ADDRESS would result in another
error:

ERROR: DIMM's DDR1 and DDR2 type can not be mixed.

This happens because initdram() routine does not explicitly
initialize dimm_populated array. This patch fixes the problem.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-01-21 08:18:37 +01:00
Felix Radensky
d98964aaac ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT
Bootstrap options G and F are reported incorrectly (G instead
of F and vice versa). This patch fixes this.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-01-21 08:18:30 +01:00
Robin Getz
f19fd87e93 Blackfin: add support for kgdb
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 20:36:09 -05:00
Mike Frysinger
cbb0cab1d9 kgdb: drop duplicate debugger_exception_handler
The debugger_exception_handler definition is the same for everyone, so use
the common one now.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-18 00:23:33 +01:00
Detlev Zundel
0f597bc2a8 mpc5xxx/cpu_init.c: Convert to IO accessors.
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-01-18 00:19:57 +01:00
Wolfgang Denk
3e3989619f Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2010-01-17 23:08:42 +01:00
Peter Tyser
64917ca389 PCIe, USB: Replace 'end point' references with 'endpoint'
When referring to PCIe and USB 'endpoint' is the standard naming
convention.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>
2010-01-17 23:06:44 +01:00
Robin Getz
03642aeee0 Blackfin: handle anomaly 05000257
Need to reload the loop counters to keep from corrupting hardware loops.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Robin Getz
b6db283440 Blackfin: keep hwtrace on CPLB miss
Crashes rarely happen in the CPLB miss handler compared to the rest of
U-Boot code, so disable hardware tracing when processing misses.  This
way a crash due to other functions will be shown properly.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
f948158f72 Blackfin: use new bfin read/write mmr helper funcs
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Mike Frysinger
313e8aacc1 Blackfin: move watchdog config check to Makefile
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
7527feef06 Blackfin: support boards with no external memory
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
dbda2c65e5 Blackfin: re-architect initcode
The single initcode function was growing unwieldy, so split it up the
distinct steps into their own function.  This should making digesting the
result much easier on people.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Mike Frysinger
b1e2c5519a Blackfin: move section length calculation to linker script
The length of the sections is fixed at link time, so let the linker do the
calculation rather than doing it ourselves at runtime.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:26 -05:00
Wolfgang Denk
02c631e6ee Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-01-12 23:30:40 +01:00
Heiko Schocher
a3f5da1bee mpc83xx: add support configure bus parking
Add support to configure bus parking mode and master in bus arbitration
configuration (ACR). Add this for the kmeter1 port:

Configure bus arbiter with recommended values from Freescale
to improve bus latency/throughput for application with
intensive QuiccEngine activity.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-07 18:39:42 -06:00
Stefan Roese
7693640acd mpc83xx: spd_sdram.c: Disable memory controller before initializing
The memory controller could already be enabled, when spd_sdram() is
called. This could be the case for example, when the SDRAM is initialized
by the JTAG debugger.

The "sync" after the register access via the accessor function is
still needed, because the macro uses the sync before the real write
is done. So until not all accesses are converted to using accessor
functions, this sync still needs to be made "manually" here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd.eu>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-01-07 18:34:30 -06:00
Dave Liu
3e731aaba3 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave
In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:50:07 -06:00
Dave Liu
1aa3d08a02 fsl-ddr: add override for the Rtt_Wr
Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:27 -06:00
Dave Liu
bdc9f7b5ea fsl-ddr: add the override for write leveling
add the override for write leveling sampling and
start time according to specific board.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:10 -06:00
Dave Liu
0a71c92c7e fsl-ddr: Fix power-down timing settings
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
   We are setting the mode register MR0[A12]='1'

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:10 -06:00
Kumar Gala
bc20f9a952 ppc/p4080: Fix reporting of PME & FM clock frequencies
We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL
backwards so we report the wrong frequency.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:10 -06:00
Kumar Gala
abc76eb6a6 ppc/85xx: Map boot page guarded for MP boot
We already map the page cache-inhibited.  There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:09 -06:00
Dave Liu
f5ecc6e027 p4080: add readback to bootpage translation window
We need to add the readback to bootpage translation LAW
to make it effect.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:09 -06:00
Kumar Gala
355f4f85e9 ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation
Now that we track which TLB CAM entries are used we can allocate
entries on the fly.  Change the SPD DDR TLB setup code to assume
we use at most 8 TLBs (or the number free, which ever is fewer).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:08 -06:00
Kumar Gala
94e9411b9d ppc/85xx: Add tracking of TLB CAM usage
We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code.  For example the SPD
DDR code today hard codes which TLB entries it uses.  We can now make
that pick entries that are free.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:08 -06:00
Kumar Gala
ee53650dad ppc/8xxx: Remove is_fsl_pci_agent
All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:07 -06:00
Kumar Gala
bcad21fda1 85xx: Add support to set DPAA (data path) devices clock frequencies
Set clock-frequency for Frame Manager 0/1 and Patter Match Engine on p4080.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:04 -06:00
Kumar Gala
178e39e199 ppc/8xxx: Don't use pci_cfg on FSL_CORENET platforms
The FSL_CORENET platforms use a completely different means to determine
which PCIe port is enabled as well as if its a host or agent/end-point.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:03 -06:00
Kumar Gala
82fd1f8da9 85xx: Add support for e500mc cache stashing
The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.

We use the following equation to set the various stash-ids:

32 + coreID*2 + 0(L1) or 1(L2)

The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:02 -06:00
Tom Rix
8f8bd565f3 USB Consolidate descriptor definitions
The header files usb.h and usbdescriptors.h have the same nameed
structure definitions for

usb_config_descriptor
usb_interface_descriptor
usb_endpoint_descriptor
usb_device_descriptor
usb_string_descriptor

These are out right duplicates in usb.h

usb_device_descriptor
usb_string_descriptor

This one has extra unused elements

usb_endpoint_descriptor

	unsigned char	bRefresh
	unsigned char	bSynchAddress;

These in usb.h have extra elements at the end of the usb 2.0
specified descriptor and are used.

usb_config_descriptor
usb_interface_descriptor

The change is to consolidate the definition of the descriptors
to usbdescriptors.h.  The dublicates in usb.h are removed.
The extra element structure will have their name shorted by
removing the '_descriptor' suffix.

So

usb_config_descriptor -> usb_config
usb_interface_descriptor -> usb_interface

For these, the common descriptor elements are accessed now
by an element 'desc'.

As an example

-	if (iface->bInterfaceClass != USB_CLASS_HUB)
+	if (iface->desc.bInterfaceClass != USB_CLASS_HUB)

This has been compile tested on MAKEALL arm, ppc and mips.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-12-20 12:47:37 +01:00
Wolfgang Denk
bb3bcfa242 Merge branch 'next' of ../next 2009-12-15 23:38:34 +01:00
Peter Korsgaard
3b887ca8ce mpc83xx: boot time regression, move LCRR setup back to cpu_init_f
Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
and LCRR bitfields) moved the LCRR assignment to after relocation
to RAM because of the potential problem with changing the local bus
clock while executing from flash.

This change unfortunately adversely affects the boot time, as running
all code up to cpu_init_r can cause significant slowdown.

E.G. on a 8347 board a bootup time increase of ~600ms has been observed:

   0.020 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.168 RS:    232
   0.172 I2C:   ready
   0.176 DRAM:  64 MB
   1.236 FLASH: 32 MB

Versus:

   0.016 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.092 RS:    232
   0.092 I2C:   ready
   0.096 DRAM:  64 MB
   0.644 FLASH: 32 MB

So far no boards have needed the late LCRR setup, so simply revert it
for now - If it is needed at a later time, those boards can either do
their own final LCRR setup in board code (E.G. in board_early_init_r),
or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
the setup in cpu_init_r.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-12-09 11:40:52 -06:00
Heiko Schocher
4b142febff common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-08 22:14:07 +01:00
Heiko Schocher
00b6d927ba 5xxx, fdt: move fdt_fixup_memory() to cpu.c file
u-boot updates, before starting Linux, the memory node in the
DTS. As this is a "standard" feature, move this functionality
to the cpu.c file for mpc5xxx and mpc512x processors.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-08 22:13:02 +01:00
Wolfgang Denk
206c00f26f Merge branch 'master' into next
Conflicts:
	lib_generic/zlib.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-07 22:47:17 +01:00
Robert P. J. Day
a93c92cdda help: Correct syntax of nandecc help output.
"nandecc" help output should not reproduce the command name, nor have
a trailing newline.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2009-12-07 22:06:51 +01:00
Wolfgang Denk
4713010adf trab: fix warning: implicit declaration of function 'disable_vfd'
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-07 21:50:18 +01:00
Wolfgang Denk
2a49bf3149 Merge branch 'master' into next
Conflicts:
	board/esd/plu405/plu405.c
	drivers/rtc/ftrtc010.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-12-05 02:11:59 +01:00
Ingo van Lil
3eb90bad65 Generic udelay() with watchdog support
According to the PPC reference implementation the udelay() function is
responsible for resetting the watchdog timer as frequently as needed.
Most other architectures do not meet that requirement, so long-running
operations might result in a watchdog reset.

This patch adds a generic udelay() function which takes care of
resetting the watchdog before calling an architecture-specific
__udelay().

Signed-off-by: Ingo van Lil <inguin@gmx.de>
2009-12-05 01:08:53 +01:00
Graeme Russ
1c409bc710 i386: Final Relocation
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:05:39 +01:00
Graeme Russ
0fc1b49ecb i386: Remove inline asm symbols from .dynsym
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:04:44 +01:00
Graeme Russ
564a9984bd i386: Rearrange Interupt Handling
In preperation for full relocation

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:04:18 +01:00
Graeme Russ
27f13075a6 i386: Fix race condition when using SC520 timers
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-12-05 01:02:58 +01:00
Jean-Christophe PLAGNIOL-VILLARD
990f569c4f avr32/hsdramc: Move conditional compilation to Makefile
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj <at> jcrosoft.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen <at> atmel.com>
2009-11-27 16:26:17 -06:00
Po-Yu Chuang
43a5f0df2f arm: A320: Add support for Faraday A320 evaluation board
This patch adds support for A320 evaluation board from Faraday. This board
uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM.
FA526 is an ARMv4 processor and uses the ARM920T source in this patch.

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
2009-11-27 16:26:17 -06:00