Commit graph

28 commits

Author SHA1 Message Date
Becky Bruce
c9315e6b4f mpc86xx: Add support to populate addr map based on BATs
If CONFIG_ADDR_MAP is enabled, update the address map
whenever we write a bat.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-02-10 00:29:49 +01:00
Becky Bruce
d35ae5a938 powerpc: Move duplicated BAT defines to mmu.h
The BAT fields are architected; there's no need for these to be in
cpu-specific files.  Drop the duplication and move these to
include/asm-ppc/mmu.h.  Also, remove the BL_xxx defines that were only
used by the alaska board, and switch to using the BATU_BL_xxx defines
used by all the other boards.  The BL_ defines previously in use
had to be shifted into the proper position for use, which was inefficient.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-02-10 00:27:40 +01:00
Kumar Gala
ecf5b98c7a 85xx: Add support to populate addr map based on TLB settings
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-19 18:20:08 -06:00
Kumar Gala
6fb1b73468 FSL DDR: Add e500 TLB helper for DDR code
Provide a helper function that board code can call to map TLBs when
setting up DDR.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:48 -05:00
Becky Bruce
d5b9b8cdb8 PPC: Add print_bats() to lib_ppc/bat_rw.c
This function prints the values of all the BAT register
pairs - I needed this for debug earlier this week; adding it to
lib_ppc so others can use it (and add it to reginfo commands
if so desired).

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-03 18:03:03 +02:00
Becky Bruce
c148f24c15 PPC: Change lib_ppc/bat_rw.c to use high bats
Currently, this code only deals with BATs 0-3, which makes
it useless on systems that support BATs 4-7.  Add the
support for these registers.

Signed-off-by: Becky Bruce <Becky.bruce@freescale.com>
2008-06-03 18:01:24 +02:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Stefan Roese
84a999b6cd ppc4xx: program_tlb now uses 64bit physical addess
This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:03 +01:00
Kumar Gala
5a9abcc317 Remove duplicate defines for ARRAY_SIZE
A few duplicate of the ARRAY_SIZE macro sneaked in since we put
the define in common.h.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-02-22 12:36:44 +01:00
Kumar Gala
44a23cfd63 85xx: Introduce new tlb API
Add a set of functions to manipulate TLB entries:
 * set_tlb() - write a tlb entry
 * invalidate_tlb() - invalidate a tlb array
 * disable_tlb() - disable a variable size tlb entry
 * init_tlbs() - setup initial tlbs based on static table

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:04:07 -06:00
Kumar Gala
2146cf5682 Reworked FSL Book-E TLB macros to be more readable
The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry.  Actually use the bit masks for these items
since they are only a single bit.

Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-09 16:25:03 -06:00
Kumar Gala
1d47273d46 Use FSL Book-E MMU macros from Linux Kernel
Grab the FSL Book-E MAS register macros from Linux.  Also added
defines for page sizes up to 4TB and removed SHAREN since it doesnt
really exist.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-09 16:25:03 -06:00
Stefan Roese
bb701283a8 Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2 2007-12-27 19:37:26 +01:00
Kumar Gala
a853d56c59 Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx
We already had defines for LAWAR_TRGT_IF_* that we should use
rather than creating new ones.  Also, added some missing defines for
PCIE targets.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Stefan Roese
483e09a223 ppc4xx: Add change_tlb function to modify I attribute of TLB(s)
This function is used to either turn cache on or off in a specific
memory area.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
5743a9207a ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup
The new function remove_tlb() can be used to remove the TLB's used to
map a specific memory region. This is especially useful for the DDR(2)
setup routines which configure the SDRAM area temporarily as a cached
area (for speedup on auto-calibration and ECC generation) and later
need this area uncached for normal usage.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16 08:53:51 +02:00
Andy Fleming
45cef612cc Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG
The other pagesz constants use one letter to specify order of
magnitude.  Also change the one reference to it in mpc8548cds/init.S

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-04-23 19:58:28 -05:00
Zang Roy-r61911
41fb7e0f1e u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board
Enable PCI function and add PEX & rapidio memory map on MPC8548CDS
board.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2007-04-23 19:58:27 -05:00
Stefan Roese
4037ed3b63 [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM support
This patch adds support for the DDR2 controller used on the
440SP and 440SPe. It is tested on the Katmai (440SPe) eval
board and works fine with the following DIMM modules:

- Corsair CM2X512-5400C4 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM)

This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:43:34 +01:00
Jon Loeliger
5f3249a0a1 Fixed leading whitespace issues.
Removed spurious LAWAR thing.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-10-13 16:47:53 -05:00
Jon Loeliger
38546f08c6 Merge branch 'mpc86xx' 2006-08-22 17:55:45 -05:00
Jon Loeliger
2c33e8a1c5 Cleanup poorly introduced whitespace. 2006-08-22 17:54:05 -05:00
Jon Loeliger
281f69ede2 Merge branch 'wd' 2006-08-09 13:36:54 -05:00
Marian Balakowicz
6c5879f380 Add support for AMCC 440SPe CPU based eval board (Yucca). 2006-06-30 16:30:46 +02:00
Jon Loeliger
debb7354d1 Initial support for MPC8641 HPCN board. 2006-04-26 17:58:56 -05:00
wdenk
0ac6f8b749 Patch by Jon Loeliger, 17 June 2004:
Completion of the 8540ADS/8560ADS updates:
Fix some PCI and Rapid I/O memory maps,
Initialize both TSEC 1 and 2,
Initialize SDRAM
Update MAINTAINER for 85xx boards and README.mpc85xxads
2004-07-09 23:27:13 +00:00
wdenk
42d1f0394b * Patches by Xianghua Xiao, 15 Oct 2003:
- Added Motorola CPU 8540/8560 support (cpu/85xx)
  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
  - Added Motorola MPC8560ADS board support (board/mpc8560ads)

* Minor code cleanup
2003-10-15 23:53:47 +00:00
wdenk
3b759bd63b Initial revision 2002-03-31 16:14:24 +00:00