Commit graph

2198 commits

Author SHA1 Message Date
Przemyslaw Marczak
fda0e27bfd exynos5: pinmux: check flag for i2c config
Some versions of Exynos5 supports High-Speed I2C,
on few interfaces, this change allows support this.
The new flag is: PINMUX_FLAG_HS_MODE

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:10:00 -07:00
Simon Glass
25ab4b0303 dm: i2c: Provide an offset length parameter where needed
Rather than assuming that the chip offset length is 1, allow it to be
provided. This allows chips that don't use the default offset length to
be used (at present they are only supported by the command line 'i2c'
command which sets the offset length explicitly).

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
2015-01-29 17:09:53 -07:00
Tom Rini
aed03faa06 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-01-26 06:42:40 -05:00
Tom Rini
306df2c824 Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2015-01-26 06:42:15 -05:00
Michal Simek
63e3cea515 ARM: zynq: List nand, qspi and jtag boot modes
Use full boot mode list in SPL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Siva Durga Prasad Paladugu
f60c6fbbc6 ARM: zynq: slcr: Dont modify the reserved bits
Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
3ad87ca182 ARM: zynq: ddrc: Setup half of memory only for ECC case
Setup half of memory from ram_size for ECC case.
All the time the same board can be configured
with or without ECC. Based on ECC case detection
use half of memory with the same configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
555c7c066f ARM: zynq: Remove empty line
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:57 +01:00
Michal Simek
c08cfc2d2c ARM: zynq: Enable the Neon instructions
Added the lowlevel_init to enable the Neon instructions.

Initially the u-boot was causing undefined instruction
exception if loaded through tcl, and working fine if loaded
through FSBL. The exception was causing in convertion formula
of given time to ticks. It was because, the Neon instructions
were disabled and hence causing the undefined exception. In
FSBL case, the FSBL was enabling the Neon instructions. Hence,
added the lowlevel_init to enable the Neon instructions.

Also enable neon instructions for non-xilinx toolchain.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-26 08:55:31 +01:00
Tom Rini
03cae7261e Merge branch 'master' of git://git.denx.de/u-boot-marvell 2015-01-25 19:05:40 -05:00
Luka Perkov
62d1e990d9 ARM: kirkwood: fix cpu info for 6282 device id
Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Stefan Roese <sr@denx.de>
2015-01-25 23:56:15 +01:00
tang yuantian
41ba57d0c7 fsl/ls1021qds: Add deep sleep support
Add deep sleep support on Freescale LS1021QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
[York Sun: Fix conflict in fdt.c]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24 09:12:32 -06:00
Alison Wang
33d2e46591 ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD boot
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are
only enabled in QSPI boot, and disabled in other boot modes.
IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot.
This patch will add fdt support for the above rules.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
tang yuantian
5699274373 ARM: HYP/non-sec: Make variable gic_dist_addr as a local one
Defining variable gic_dist_addr as a globe one prevents some
functions, which use it, from being used before relocation
which is the case in the deep sleep resume process on Freescale
SoC platforms.
Besides, we can always get the GIC base address by calling
get_gicd_base_address() without referring gic_dist_addr.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Ruchika Gupta
0181937fa3 crypto/fsl: Add fixup for crypto node
Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used across arm and
powerpc platforms having crypto node.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
[York Sun: Fix commit message indentation]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Tom Rini
3b95288a2a Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-01-23 10:22:29 -05:00
Masahiro Yamada
ee94ee3464 ARM: UniPhier: remove non-sense inline directives
The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:51:44 +09:00
Masahiro Yamada
ec79c79824 ARM: UniPhier: add static to local functions
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:51:21 +09:00
Masahiro Yamada
448437496b ARM: UniPhier: fix IECTRL set code for PH1-Pro4
For PH1-Pro4, the bit 6 of the IECTRL must be set.  It is the only
available bit in this register.  There is no effect of the write
access to the other bits.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:50:57 +09:00
Masahiro Yamada
061ae4c0bb ARM: UniPhier: describe init_page_table shorter
The assembly directive ".rept ... .endr" allows us to write the
init_page_table much shorter.  To make things further simpler,
set the text and stack area as Normal Memory, and the other sections
as Device attribute.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:50:21 +09:00
Masahiro Yamada
89a7c773ea ARM: UniPhier: fix comments in SoC Glue init function
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:49:57 +09:00
Hans de Goede
dacc0881ac sun9i: Add sun9i (A80) clock setup support
Add initial sun9i (A80) clock setup support, enough to get the uart + mmc
going.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
22b618346a sunxi: Drop pll6 setting from clock_init_uart
As the comment says now that we have SPL support this is no longer necessary,
as PLL6 is already setup with the exact same parameters by the SPL.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
b56f6e2b4e sunxi: Restore lowlevel_init usage
2 recent sunxi changes have removed the usage of lowlevel_init by moving some
code around and then setting CONFIG_SKIP_LOWLEVEL_INIT.
This is problematic for 2 reasons:

1) It does not just stop s_init from being called, it also stops
cpu_init_cp15 from getting called, which is undesirable.

2) We want u-boot.bin to be usable standalone, without SPL, some people e.g.
use an upstream u-boot.bin together with Allwinner's boot0 loader. So
u-boot.bin must (re)initialize the gpios, timer, etc.

This commit restores the lowlevel_init / s_init usage, while keeping the
changes to no longer use the global-data (gd) struct in the SPL.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-21 10:46:28 -05:00
Simon Glass
80caacf9de zynq: Remove reference to gdata
The global_data pointer (gd) has already been set before board_init_f()
is called. We should not assign it again. We should also not use gdata since
it is going away.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-20 10:15:15 -05:00
Bo Shen
765ece8b13 ARM: atmel: sama5d4: add usb device initial code
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-01-19 15:02:44 +01:00
Heiko Schocher
99197a9e31 arm, arm926ejs: make thumb mode compileable
in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c
when enabling CONFIG_SYS_THUMB_BUILD:

{standard input}: Assembler messages:
{standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0'
{standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'

so, if caches are disabled, do not use this command on arm926ejs.
used on at91 in SPL, to reduce size of SPL.

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-01-19 12:49:26 +01:00
Simon Glass
2b7c0f3081 sunxi: Drop use of lowlevel_init()
This does nothing now, so drop it. We have SPL anyway to do our low-level
init.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-16 14:52:53 -05:00
Simon Glass
f630974ccb sunxi: Move SPL s_init() code to board_init_f()
The current sunxi implementation uses gdata, which is going away. It also
sets up DRAM before board_init_f() in SPL.

There is really no reason to do much in s_init() since board_init_f() is
called immediately afterwards. The only change is that we need our own
implementation of board_init_f() which sets up DRAM before the BSS (which
is in DRAM) is cleared.

The s_init() code runs once for SPL and again for U-Boot proper. We
shouldn't need to init the clock/timer/gpio/i2c init twice, so just have it
in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-16 14:52:52 -05:00
Tom Rini
a6b541b090 TI ARMv7: Don't use GD before crt0.S has set it
Prior to this change we set the gd pointer early so that we can store
data in it.  This becomes problematic for DM changes as well as being
odd in general.  Re-work the code paths so that we don't need to set the
gd pointer so early and instead can rely upon the normal setting of it.

In order to do this we do need to move certain calls from s_init into
spl_board_init(), mainly preloader_console_init and
save_omap_boot_params.

Tested on: Beaglebone Black, AM43xx GP EVM, Beagleboard, Beagleboard xM,
OMAP5 uEVM, DRA7xx EVM
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-16 14:52:52 -05:00
Tom Rini
ab77f24119 Merge branch 'master' of git://git.denx.de/u-boot-ti 2015-01-16 10:25:01 -05:00
Michal Simek
f1075aedd2 ARM: armv8: Fix typo in commentary
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-14 11:37:39 -05:00
Evgeni Dobrev
9637c4b2dd Add support for Seagate BlackArmor NAS220
Add support for Seagate BlackArmor NAS220

Signed-off-by: Evgeni Dobrev <evgeni@studio-punkt.com>
2015-01-14 11:37:39 -05:00
Hans de Goede
a90e77dbeb sunxi: usbc: Add support for usb-vbus0 controller by axp drivebus pin
The axp221 / axp223's N_VBUSEN pin can be configured as an output rather
then an input, and this is used on some boards to control usb-vbus0, add
support for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Hans de Goede
4458b7a6e1 sunxi: usbc: Add support for usb0 to the common usbc code
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Hans de Goede
0eccec4ef1 sunxi: Move usb-controller init code out of ehci-sunxi.c for reuse for otg
Most of the usb-controller init code found in ehci-sunxi.c also is necessary
to init the otg usb controller, so move it to a common place.

While at it also update various #ifdefs / defines for sun8i support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Jan Kiszka
05c4bd3ec3 sun7i: Move psci_arch_init close to text_end
"adr rX, text_end" only works if the label is close. Adding further code
to the other functions will prevent this. So move the containing
function close to label. No functional change.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Jan Kiszka
602fa46c2c sun7i: Add support for taking CPUs offline via PSCI
Based on the original version by Marc Zyngier. It adds a psci_cpu_off
implementation for the A20 SoC. The mechanism works by first preparing
the calling CPU to go offline (disable and flush cache, disable SMP),
then requesting CPU 0 to pull the plug. The request is sent as FIQ on
SGI15.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Hans de Goede
25508ab26c sunxi: Fix PLL1 running at half speed on sun8i
PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Siarhei Siamashka
c3d2b963c6 sunxi: Fix buggy sun6i/sun8i DRAM size detection logic
After reboot, reset or even short power off, DRAM typically retains
the old stale data for some period of time (for this type of memory,
the bits of data are stored in slowly discharging capacitors).

The current sun6i/sun8i DRAM size detection logic, which is
inherited from the Allwinner code, relies on using a large magic
signature with the hope that it is unique enough and unlikely to
ever accidentally match this leftover garbage data in RAM. But
this approach is inherently unsafe, as can be demonstrated using
the following test program:

/***** A testcase for reproducing the problem ******/

void main(int argc, char *argv[])
{
    size_t size, i;
    uint32_t *buf;
    /* Allocate the buffer */
    if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) ||
                    !(buf = malloc(size))) {
        printf("Need buffer size in MiB as a cmdline argument\n");
        exit(1);
    }
    /* Fill it with the Allwinner DRAM "magic" values */
    for (i = 0; i < size / 4; i++)
        buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64;
    /* Try to reboot */
    system("reboot");
    /* And wait */
    for (;;) {}
}
/***************************************************/

If this test program is run on the device (giving it a large
chunk of memory), then the DRAM size detection logic in u-boot
gets confused after reboot and fails to initialize DRAM properly.

A better approach is not to rely on luck and abstain from making
any assumptions about the properties of the leftover garbage
data in RAM. Instead just use a more reliable code for testing
whether two different addresses refer to the same memory location.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-14 14:56:37 +01:00
Hans de Goede
08fd1479c7 sun8i: Add dram initialization support
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
5665f50e81 sunxi: Fill memory before comparing it when doing dram init on sun6i
The sun8i boot0 code fills the DRAM with a "random" pattern before comparing
it at different offsets to do columns, etc. detection. The sun6i boot0 code
does not do it, instead relying on the memory contents being random enough
to begin with for the memcmp to properly detect the wrap-around address, iow
it is working purely by chance. Since our sun6i dram code was modelled after
the boot0 code it contained the same issue.

This commit fixes this by filling the memory with a unique, distinct pattern.

The new mctl_mem_fill function this introduces is added as an inline helper
in dram.h, so that it can be shared with the sun8i dram code.

While at it move mctl_mem_matches to dram.h for re-use in sun8i too.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
07f4fe7d7d sunxi: Move await_completion dram helper to dram.h
The await_completion helper is already copy pasted between the sun4i and sun6i
dram code, and we need it for sun8i too, so lets make it an inline helper in
dram.h, rather then adding yet another copy.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
1aac47bd1b sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them
Our old hardcoded k and m values are based on PLL5 being configured in steps
of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the
DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i)
the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps.

This commit adjusts clock_set_pll5 to automatically select the best k and m
depending on the requested clk rate.

Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
5af741f1e9 sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()
The sun8i dram code sometimes wants to enable sigma delta mode,
add a parameter to allow this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
bdcdf84631 sunxi: axp221: Add axp223 support
The axp223 appears to be the same as the axp221, except that it uses the
rsb to communicate rather then the p2wi. At least all the registers we use
are 100% the same.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
66ebea06f7 sunxi: Add support for the rsb (Reduced Serial Bus)
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.

This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
ce881076fc sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/
The p2wi interface is only available on sun6i, adjust the gpio pinmux and
base address defines for it to reflect this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Jan Kiszka
3f6242eb30 sunxi: Align PSCI stack calculation to comment
0x400 is true 1K.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
cac5b1cc0d sunxi: Add sunxi_get_sid helper function
On sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a helper function to abstract this away.

This makes our MAC address generation code also work on sun6i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00