Commit graph

20236 commits

Author SHA1 Message Date
Heiko Stuebner
ba421b96a2 rockchip: rk3368: sync down rk3368-lion board devicetree from Linux
This brings the actual rk3368-lion devicetree files from Linux 5.10
instead of using something separate.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30 16:53:00 +08:00
Heiko Stuebner
5aefa4af29 rockchip: rk3368: sync main rk3368 dtsi from Linux
This is the state as of v5.10 + the recently added timer0 phandle
targetted at the 5.12 merge window.

With this the non-mainline nodes like the dmc move to a separate
rk3368-u-boot.dtsi that is included from the board-specific
-u-boot.dtsi files, similar to how rk3399 does this.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30 16:53:00 +08:00
Heiko Stuebner
ca7bb9dde7 rockchip: rk3368: move STACK_R_ADDR address and into Kconfig
With the STACK_R_ADDR at 0x600000 (6MB) we're competing with
with the loading address of either u-boot or atf parts, so move
that away to 0x4000000 (64MB) similar to rk3399.

Only lion currently sets that at all but not sheep the second
rk3368 board, so just move that to the Kconfig for rk3368 similar
to rk3399 as well.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30 16:53:00 +08:00
Heiko Stuebner
53e14aa734 rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000
To prevent running out of memory, increase SYS_MALLOC_F_LEN to 0x4000
similar to what rk3399 uses.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30 16:53:00 +08:00
Heinrich Schuchardt
e5021221db sandbox: define __dyn_sym_start, dyn_sym_end
On RISC-V the symbols __dyn_sym_start, dyn_sym_end are referenced in
efi_runtime_relocate().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-27 16:26:48 +13:00
Simon Glass
80a4570c99 x86: coral: Show memory config and SKU ID on startup
Provide the model information through sysinfo so that it shows up on
boot. For memconfig 4 pins are provided, for 16 combinations. For SKU
ID there are two options:

   - two pins provided in a ternary arrangement, for 9 combinations.
   - reading from the EC

Add a binding doc and drop the unused #defines as well.

Example:

   U-Boot 2021.01-rc5

   CPU:   Intel(R) Celeron(R) CPU N3450 @ 1.10GHz
   DRAM:  3.9 GiB
   MMC:   sdmmc@1b,0: 1, emmc@1c,0: 2
   Video: 1024x768x32 @ b0000000
   Model: Google Coral (memconfig 5, SKU 3)

This depends on the GPIO series:

   http://patchwork.ozlabs.org/project/uboot/list/?series=228126

Signed-off-by: Simon Glass <sjg@chromium.org>

Acked-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-27 16:26:48 +13:00
Simon Glass
c119528a1d sandbox: Correct uninit conflict
It is not possible to remove the state before driver model is uninited,
since the devices are allocated in the memory buffer. Also it is not
possible to uninit driver model afterwards, since the RAM has been
freed.

Drop the uninit altogether, since it is not actually necessary.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:31 +13:00
Simon Glass
529d5f96cf cpu: Rename SPL_CPU_SUPPORT to SPL_CPU
The _SUPPORT suffix is from an earlier time and interferes with use of
the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix.

Tidy up the TODO that prompted this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:31 +13:00
Simon Glass
5d8c37910d sandbox: Only delete the executable if requested
At present sandbox removes its executable after failing to run it,
since there is no other way that it would get cleaned up.

However, this is actually only wanted if the image was created within
sandbox. For the case where the image was generated by the build system,
such as u-boot-spl, we don't want to delete it.

Handle the two code paths accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:31 +13:00
Simon Glass
70f5c99d60 x86: coreboot: Don't setup MTRR when booting from coreboot
This currently hangs and it is not necessary in any case. Drop the code
when booting from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:31 +13:00
Simon Glass
9087e468c7 x86: fsp: Don't notify if booted from coreboot
When booting from coreboot there is no need to notify the FSP of anything,
since coreboot has already done it. Nor it is possible, since the FSP
details are not provided by coreboot.

Skip it in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:30 +13:00
Simon Glass
8657989f29 x86: coral: Fall back to coreboot video when FSP missing
When booting from coreboot the FSP video information is no-longer
available. Enable the coreboot driver so that we can get some sort of
display in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:30 +13:00
Simon Glass
51de94dfe4 x86: coral: Allow init of debug UART in U-Boot proper
At present the debug UART is only set up in SPL, on the assumption that
the boot flow will always pass through there. When booting from coreboot,
SPL is not used, so the debug UART is not available.

Move the code into a common place so that it can be used in U-Boot proper
also. Add the required init to start_from_spl.S as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:30 +13:00
Simon Glass
2018a33cb7 x86: coral: Avoid build error with !CONFIG_ACPIGEN
When CONFIG_ACPIGEN is not enabled the CPU code does not build. Fix this
by moving things around.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:30 +13:00
Simon Glass
937175ee72 x86: fsp: Don't enable FSP graphics if booted from coreboot
This driver cannot work when booted from coreboot, since the FSP
information is not available. Disable it in that case, so that the
coreboot video driver can be used instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:30 +13:00
Simon Glass
e7bae8283f x86: Allow installing an e820 when booting from coreboot
Move this code into a generic location so that it can be used by other x86
boards which want to boot from coreboot. Also ensure that this is called
if booting from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:29 +13:00
Simon Glass
1058ab37f7 x86: coreboot: Update parsing of the latest sysinfo
Quite a few new tag types have been added over the years. Bring these into
U-Boot so that all required tags can be parsed.

Add a proper comment to struct sysinfo_t while we are here, since many of
the meanings are not obvious.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:59 +13:00
Simon Glass
68e03ca21a x86: Move coreboot sysinfo parsing into generic x86 code
It is useful to be able to parse coreboot tables on any x86 build which is
booted from coreboot. Add a new Kconfig option to enable this feature and
move the code so it can be used on any board, if enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:59 +13:00
Simon Glass
f9f06e628e x86: coreboot: Sync up timestamp codes
Add new timestamp codes that are present in coreboot, so that we can decode
these in U-Boot.

At present TS_U_BOOT_START_KERNEL is used twice. It should only be used
just before jumping to Linux, so update the other call site to use
TS_START_KERNEL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:37 +13:00
Simon Glass
17753b0382 x86: Move coreboot timestamp info into coreboot_tables.h
This all relates to the sysinfo structure provided by coreboot. Put the
timestamp definitions into the same file as the others. Tidy up a few
comments at the same time.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:37 +13:00
Simon Glass
e35b6497f4 x86: Make coreboot sysinfo available to any x86 board
It is possible to boot U-Boot for chromebook_coral either 'bare metal' or
from coreboot. In the latter case we want to provide access to the coreboot
sysinfo tables. Move the definitions into a file available to any x86
board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:37 +13:00
Simon Glass
5536f1285f cbfs: Allow access to CBFS without a header
In some cases CBFS does not start with a header but is just a collection
of files. It is possible to support this so long as the size of the CBFS
is provided.

Update the cbfs_init_mem() function to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:37 +13:00
Simon Glass
ac7765017a x86: coral: Update the SD card-detect GPIO
Since the recent bug fix, it doesn't matter which GPIO phandle is used so
long as the GPIO number is right. Still, we may as well use the correct
one to avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-03-27 13:59:36 +13:00
Simon Glass
041089fe93 x86: coral: Put the eMMC first
At present the eMMC device does not have an alias so it appears after
the SD card which is device 1. There is no device 0 which is odd.

Make the eMMC device be the first one. Update the boot script to use the
new device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-03-27 13:59:36 +13:00
Vincent Stehlé
619a81516d sandbox: dtsi: add rng
Having an rng in the sandbox is useful not only for tests but also for e.g.
UEFI. Therefore, copy the rng node from test.dts to sandbox.dtsi.

In the case of UEFI, it can then be verified with `efidebug dh' that a
"Random Number Generator" protocol is indeed present.

This also fixes the following `bootefi' error:

  Missing RNG device for EFI_RNG_PROTOCOL

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:36 +13:00
Simon Glass
cad7b6b251 x86: dts: Drop unused CONFIG_SPL
This cannot be used since the previous #elif has already dealt with SPL.
Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:10 +13:00
Simon Glass
cb88ec7cab x86: Make use of binman expanded entries
We don't need to spell out the separate pieces of U-Boot phase binaries
anymore. Revert to using the simple entry and let binman do the expansion
itself as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
98ed0ae2cc x86: apl: Use read-only SPL and new of-platdata
With Apollo Lake, SPL is placed in read-only memory. Set this new option
so that OF_PLATDATA_INST can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
541b2adf08 x86: coral: Drop TPM and ACPI interrupts from TPL
These devices are not actually built in TPL but are currently active in
the TPL devicetree. For of-platdata-inst this means that we will try to
generate devices for them, which fails.

Update them to be active only in U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
5384ea96ce x86: Don't include reset driver in SPL
We don't normally need this driver in TPL/SPL, so drop it for now. It can
be enabled by individual boards if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
1d3daaa681 x86: Support a fake PCI device with of-platdata-inst
With TPL we don't need full PCI support and it adds to code size. Instead,
a simple_bus driver is good enough to be able to read and write the PCI
config and do a little basic setup.

So at present there are two drivers in U-Boot called pci_x86. One is in
UCLASS_PCI, used in SPL and U-Boot proper. The other is in
UCLASS_SIMPLE_BUS and used only in TPL.

Add a tag to tell dtoc about this, so it knows which one to use when
generating the devices and uclasses.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
763ce51bc3 x86: itss: Tidy up bind() for of-platdata-inst
With the standard of-platdata we must fix up driver_data manually. With
of-platadata-inst this is not necessary, since it is added to the device
by dtoc.

Update the code to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
a65c35ed77 x86: apl: Tell of-platdata about a required header file
This enum is needed to generate build-time devices. Tell dtoc where to
find the header, to avoid compile errors in the generated code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
8d0defa44b x86: apl: Fix the header order in pmc
The dm.h header should come first. In fact it needs to, since otherwise
the driver model definitions are not available to dt-structs.h

Fix this, since it causes problems with OF_PLATDATA_INST.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
72db28ee68 x86: Define a region for device priv/plat data
Collect this together in one place, so driver model can access set it up
in a new place if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
d5cc19288e sandbox: Define a region for device priv/plat data
Collect this together in one place, so driver model can access set it up
in a new place if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:09 +13:00
Simon Glass
3a825d3fa7 Revert "sandbox: Disable I2C emulators in SPL"
With recent changes this can be supported again. Add it back.

This reverts commit d85f2c4f29.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
e62ad9c867 sandbox: i2c: Move platdata structs to header files
At present the structs used by these drivers are declared in the C files
and so are not accessible to dtoc. Move them to header files, as required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
8813986dfd clk: sandbox: Create a special fixed-rate driver
Create a version of this driver for sandbox so that it can use the
of-platdata struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
cc7ffd3adc clk: sandbox: Move priv/plat data to a header file
At present the structs used by this driver are not accessible outside it,
so cannot be used with OF_PLATDATA_INST. Move them to a header file to
fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26 17:03:08 +13:00
Simon Glass
b5e514a6ab sandbox: Drop debug message in os_spl_to_uboot()
This is not needed in normal operation. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-03-22 19:23:28 +13:00
Simon Glass
c4085d733b sandbox: i2c: Rename driver names to work with of-platdata
Some of these do not follow the rules. Make sure the driver name matches
the compatible string in all cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:27 +13:00
Simon Glass
23f40a3abf sandbox: Make sandbox,emul more conventional
At present this property is a phandle but does not have a #xxx-cells
property to match it. Add one so that is works the same as gpio and clock
phandles.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:27 +13:00
Heinrich Schuchardt
4a2a78ca5c sandbox: enable cros-ec-keyb in test.dtb
Currently keyboard input fails in the GUI window opened by

    ./u-boot -T -l

Add the missing include to test.dts.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-22 19:23:26 +13:00
Weijie Gao
f4f478be4c board: mt7629: enable compression of u-boot to reduce the size of final image
This patch makes use of the decompression mechanism implemented for mt7628
previously to reduce the total image size. Binman will be also removed.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-03-20 16:24:27 -04:00
Weijie Gao
e8b98f0270 dts: mt7629: enable JTAG pins by default
The EPHY LEDs belongs to the built-in FE switch of MT7629, which is barely
used. These LED pins on reference boards are used as JTAG socket. So it's
a good idea to change the default state to JTAG, and this will make it
convenience for debugging.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-03-20 16:24:27 -04:00
Fabien Parent
e96bedf146 board: Add MT8183 pumpkin board support
Add the MT8183 pumpkin board support.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-03-20 16:24:27 -04:00
Fabien Parent
18380437c1 ARM: mediatek: Add MT8183 support
Add the MT8183 SoC support.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-03-20 16:24:27 -04:00
Fabien Parent
86e07d59ee board: mediatek: rename pumpkin board into mt8516
More than one pumpkin board has been made with different MediaTek SoCs.
Rename the pumpkin board to follow the naming convention of all
other MediaTek boards and also to not be confusing when other pumpkin
boards will be added in follow-up commits.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-03-20 16:24:26 -04:00
Lad Prabhakar
9e346340d7 board: silinux: Enable recovery SPL for EK874 board
Enable building SPL for EK874 board which is based on R8A774C0 SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-03-16 20:09:30 +01:00