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https://github.com/AsahiLinux/u-boot
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ARM: mediatek: Add MT8183 support
Add the MT8183 SoC support. Signed-off-by: Fabien Parent <fparent@baylibre.com>
This commit is contained in:
Fabien Parent
Tom Rini
parent
21f593214b
commit
18380437c1
5 changed files with 367 additions and 0 deletions
274
arch/arm/dts/mt8183.dtsi
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274
arch/arm/dts/mt8183.dtsi
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@ -0,0 +1,274 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Copyright (C) 2021 BayLibre, SAS
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* Author: Ben Ho <ben.ho@mediatek.com>
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* Erin Lo <erin.lo@mediatek.com>
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* Fabien Parent <fparent@baylibre.com>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "mediatek,mt8183";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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enable-method = "psci";
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capacity-dmips-mhz = <741>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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enable-method = "psci";
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capacity-dmips-mhz = <741>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x002>;
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enable-method = "psci";
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capacity-dmips-mhz = <741>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x003>;
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enable-method = "psci";
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capacity-dmips-mhz = <741>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x101>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x102>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x103>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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};
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clk26m: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt8183-wdt",
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"mediatek,wdt";
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reg = <0 0x10007000 0 0x100>;
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status = "disabled";
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};
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <4>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c100000 0 0x200000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
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ppi-partitions {
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ppi_cluster0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
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};
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ppi_cluster1: interrupt-partition-1 {
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affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
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};
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};
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};
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sysirq: interrupt-controller@c530a80 {
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compatible = "mediatek,mt8183-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x0c530a80 0 0x50>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt8183-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt8183-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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apmixedsys: syscon@1000c000 {
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compatible = "mediatek,mt8183-apmixedsys", "syscon";
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reg = <0 0x1000c000 0 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt8183-uart",
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"mediatek,hsuart";
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reg = <0 0x11002000 0 0x1000>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clock-frequency = <26000000>;
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clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8183-mmc";
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reg = <0 0x11230000 0 0x1000>,
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<0 0x11f50000 0 0x1000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
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<&infracfg CLK_INFRA_MSDC0>,
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<&infracfg CLK_INFRA_MSDC0_SCK>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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u3phy: usb-phy@11f40000 {
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compatible = "mediatek,generic-tphy-v2";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "okay";
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u2port0: usb-phy2@11f40000 {
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reg = <0 0x11f40000 0 0x700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u3port0: usb-phy3@11f40700 {
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reg = <0 0x11f40700 0 0x900>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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usb: usb@11200000 {
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compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
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reg = <0 0x11200000 0 0x3e00>,
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<0 0x11203e00 0 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
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phys = <&u2port0 PHY_TYPE_USB2>;
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clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
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<&infracfg CLK_INFRA_USB>;
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clock-names = "sys_ck", "ref_ck";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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ssusb: ssusb@11200000 {
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compatible = "mediatek,ssusb";
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reg = <0 0x11200000 0 0x3e00>;
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reg-names = "mac";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
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status = "disabled";
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};
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usb_host: xhci@11200000 {
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compatible = "mediatek,mtk-xhci";
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reg = <0 0x11200000 0 0x1000>;
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reg-names = "mac";
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
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<&infracfg CLK_INFRA_USB>;
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clock-names = "sys_ck", "ref_ck";
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status = "disabled";
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};
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};
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};
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};
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@ -42,6 +42,15 @@ config TARGET_MT7629
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including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
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switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
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config TARGET_MT8183
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bool "MediaTek MT8183 SoC"
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select ARM64
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help
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The MediaTek MT8183 is a ARM64-based SoC with a quad-core Cortex-A73 and
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a quad-core Cortex-A53. It is including UART, SPI, USB3.0 dual role,
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SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
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and LPDDR4 options.
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config TARGET_MT8512
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bool "MediaTek MT8512 M1 Board"
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select ARM64
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@ -7,5 +7,6 @@ obj-$(CONFIG_MT8512) += mt8512/
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obj-$(CONFIG_TARGET_MT7622) += mt7622/
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obj-$(CONFIG_TARGET_MT7623) += mt7623/
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obj-$(CONFIG_TARGET_MT7629) += mt7629/
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obj-$(CONFIG_TARGET_MT8183) += mt8183/
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obj-$(CONFIG_TARGET_MT8516) += mt8516/
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obj-$(CONFIG_TARGET_MT8518) += mt8518/
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3
arch/arm/mach-mediatek/mt8183/Makefile
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3
arch/arm/mach-mediatek/mt8183/Makefile
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# SPDX-License-Identifier: GPL-2.0
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obj-y += init.o
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80
arch/arm/mach-mediatek/mt8183/init.c
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80
arch/arm/mach-mediatek/mt8183/init.c
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@ -0,0 +1,80 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Copyright (C) 2021 BayLibre, SAS
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* Author: Fabien Parent <fparent@baylibre.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <ram.h>
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#include <asm/arch/misc.h>
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#include <asm/armv8/mmu.h>
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#include <asm/sections.h>
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#include <asm/system.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/mt8516-clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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int ret;
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ret = fdtdec_setup_memory_banksize();
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if (ret)
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return ret;
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = gd->ram_base;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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int mtk_pll_early_init(void)
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{
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return 0;
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}
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int mtk_soc_early_init(void)
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{
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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psci_system_reset();
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}
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int print_cpuinfo(void)
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{
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printf("CPU: MediaTek MT8183\n");
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return 0;
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}
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static struct mm_region mt8183_mem_map[] = {
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{
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/* DDR */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
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}, {
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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0,
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}
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};
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struct mm_region *mem_map = mt8183_mem_map;
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