With DM I2C, the EEPROM bus has been correctly configured in
eeprom_execute_command() already. Do not reconfigure it here
with hard-coded bus number again.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This patch replaces use fdtdec_get_addr with simpler dev_read_addr().
fdtdec_get_addr doesn't work properly on ZynqMP-based (64bit) system. Although
not confirmed, it could be related to the fact, that quoting the documentation,
"This variant hard-codes the number of cells used to represent the address and
size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t)".
Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Once request is sent, and before receiving a response, the delay is required.
This patch fixes missing delay for before first response try.
Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
If the maximum number of wake-up attempts is exceeded, return -ETIMEDOUT.
Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Documentation:
* Fix documentation of FIP creation for Amlogic boards
* Update Nokia RX-51 QEMU documentation
* Add Raspberry Pi documentation
UEFI:
* Fix booting via short form device paths
* Support short form device paths in 'efidebug boot add'
* Fix ESP detection for capsule updates
* Allow ACPI table usage even if device-tree exists - ignore DT
* OP-TEE based GetVariable(): return attributes when buffer too small
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmI3UAIACgkQxIHbvCwF
GsRopA/7BLiFUFayMnVL3qCLZKrceKSbz76zSs18zMab4U7FWEiWTLfqhV4PSgT+
SfcpOCFsodRIGvNKwm/RpVSpwj7NPINUL29Hn70ojN0ckuJZNBj8ILflr7y6iuCX
OI48rezhvnOMKk0F2JNFCQDzPYJVKm7Ej1M+CfVCuL+iQNEk4l9FI/pgnT8at5D/
TcmUQIvqEj6wTv2XaT59AKm85R0r14NJHNRgNEEwgeReiZZ/cxK9I/jYTMFxWK0r
uOEB1jrsRKnTMq3fgg9fOZRQvjavqoqe0evVtBfrkBpYP48AK9c9vXSBfCSUnygl
lM+JS6keWaKeOH4605UHhxaFjAoW7VEH+a6jubbDoNNTUspRGpY6UViAc7O16DDK
AjZN6uoUkeREFMokvHsgsh63cRj2WkKnildAIcnRyLhqQuHe+QS8ndiOSV4Q0peO
ifT8BFF4loN2ttAViKNYeM6ydBabjmwJiuzuUG0tyxiYDXLS0/ErNp7aUwTgc/qP
1E46PS+f6sZG2oiNk5L2MP689wEBgZpjSck4aH3ba+UrtGXSh/YC5ERaN1Zm7K5M
GJ3UOL+G+o0Is4gYgp7tvizVfu+8FIC/ilOndmgtwdRoUYrUA2ePx7WPvArnHLc3
rymR7IJ1yCD5RjVB3lA6eL76ORKNRBe3Gs7zGRK5jg55pw3MFSo=
=Kn/h
-----END PGP SIGNATURE-----
Merge tag 'efi-2022-04-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2022-04-rc5
Documentation:
* Fix documentation of FIP creation for Amlogic boards
* Update Nokia RX-51 QEMU documentation
* Add Raspberry Pi documentation
UEFI:
* Fix booting via short form device paths
* Support short form device paths in 'efidebug boot add'
* Fix ESP detection for capsule updates
* Allow ACPI table usage even if device-tree exists - ignore DT
* OP-TEE based GetVariable(): return attributes when buffer too small
The tools dtbdump.efi and initrddump.efi are useful for Python testing even
if CONFIG_EFI_SELFTEST=n.
Don't clear the screen as it is incompatible with Python testing.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The block IO protocol may be installed on any handle. We should make
no assumption about the structure the handle points to.
efi_disk_is_system_part() makes an illegal widening cast from a handle
to a struct efi_disk_obj. Remove the function.
Fixes: Fixes: 41fd506842 ("efi_loader: disk: add efi_disk_is_system_part()")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The GUID of partitions is sufficient for identification and will stay
constant in the lifetime of a boot option. The preceding path of the
device-path may change due to changes in the enumeration of devices.
Therefore it is preferable to use the short-form of device-paths in load
options. Adjust the 'efidebug boot add' command accordingly.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The boot manager must support loading from boot options using a short-form
device-path, e.g. one where the first element is a hard drive media path.
See '3.1.2 Load Options Processing' in UEFI specification version 2.9.
Fixes: 0e074d1239 ("efi_loader: carve out efi_load_image_from_file()")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Let function efi_dp_find_obj() additionally check if a given protocol is
installed on the handle relating to the device-path.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
efi_dp_find_obj() should not return any handle with a partially matching
device path but the handle with the maximum matching device path.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Starting UEFI Spec 2.8 we must fill in the variable attributes when
GetVariable() returns EFI_BUFFER_TOO_SMALL and Attributes is non-NULL.
This code was written with 2.7 in mind so let's move the code around a
bit and fill in the attributes EFI_BUFFER_TOO_SMALL is returned
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
For targets that enable ACPI, we should not pass Device Trees into
the payload. However, our distro boot logic always passes the builtin
DT as an argument.
To make it easy to use ACPI with distro boot, let's just ignore the DT
argument to bootefi when ACPI is enabled. That way, we can successfully
distro boot payloads on ACPI enabled targets.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Add documentation about the different configuration files for the
RaspberryPi board family.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
There is no CONFIG_UEFI_SECURE_BOOT, and there was never any.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Add section how to run U-Boot in n900 qemu machine.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
It add documentation on licencing & provides links to the amlogic-boot-fip
pre-built files collections.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Fix documentation path in deprecated warning message about device
driver.
Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Fix documentation path in warning message about deprecated device driver.
Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
A comma at the end of a line gives sometimes strange
effects in combination with some code formatters,
so replace a comma by a semicolon in the sdram_rk3188.c
and sdram_rk3288.c files.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
U-Boot can be chainloaded from vendor firmware on ARM64 chromebooks from
a GPT partition (roughly the same as in doc/chromium/chainload.rst), but
an appropriate image header must be built-in to the U-Boot binary by
enabling LINUX_KERNEL_IMAGE_HEADER.
This header has a field for an image load offset from 2MiB alignment
which must also be customized through LNX_KRNL_IMG_TEXT_OFFSET_BASE.
Set it equal to SYS_TEXT_BASE by default for Rockchip boards, which
happens to make this offset zero and works fine on chromebook_kevin
both for chainloading and bare-metal use.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove double semi-colon that has been forgotten while adding the
driver. This is only a style fix since it doesn't change the
functionality of the driver.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This is very useful to access the LibreComputer eMMC as removable
storage from a PC (e.g. like so `ums 0 mmc 0`). It has been tested as
working on my Renegade board.
Signed-off-by: Leonidas P. Papadakos <papadakospan at gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The current files and directories with wildcard patterns for
Rockchip patches in MAINTAINERS is not always complete.
Add the regex for DT related files and a generic regex for
catching some other forgotten cases, so that the maintainers
receive all Rockchip related patches.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for Kevin, an RK3399-based convertible chromebook that is
very similar to Bob. This patch is mostly based on existing support for
Bob, with only minor changes for Kevin-specific things.
Unlike other Gru boards, coreboot sets Kevin's center logic to 925 mV,
so adjust it here in the dts as well. The rk3399-gru-kevin devicetree
has an unknown event code reference which has to be defined, set it
to the Linux counterpart. The new defconfig is copied from Bob with the
diffconfig:
DEFAULT_DEVICE_TREE "rk3399-gru-bob" -> "rk3399-gru-kevin"
DEFAULT_FDT_FILE "rockchip/rk3399-gru-bob.dtb" -> "rockchip/rk3399-gru-kevin.dtb"
VIDEO_ROCKCHIP_MAX_XRES 1280 -> 2400
VIDEO_ROCKCHIP_MAX_YRES 800 -> 1600
+TARGET_CHROMEBOOK_KEVIN y
With this Kevin can boot from SPI flash to a usable U-Boot prompt on the
display with the keyboard working, but cannot boot into Linux for
unknown reasons.
eMMC starts in a working state but fails to re-init, microSD card works
but at a lower-than-expected speed, USB works but causes a hang on
de-init. There are known workarounds to solve eMMC and USB issues.
Cc: Marty E. Plummer <hanetzer@startmail.com>
Cc: Simon Glass <sjg@chromium.org>
[Alper: commit message, resync config with Bob, update MAINTAINERS,
add to Rockchip doc, add Kconfig help message, set regulator]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This patch enables some configs that should be working on the Bob board,
based on what is observed to work on the Kevin board.
The Bob board uses an Embedded DisplayPort panel compatible with the
simple panel and Rockchip eDP drivers. Its backlight is controlled by
the Chromium OS Embedded Controller Pulse Width Modulator. Enable these
for the board.
Also set VIDEO_ROCKCHIP_MAX_{XRES,YRES} to 1280x800, the resolution of
its panel. This had to be done for the Kevin board, but it's untested if
this is actually necessary for Bob.
The Rockchip video driver needs to assert/deassert some resets, so also
enable the reset controller. RESET_ROCKCHIP defaults to y for this board
when DM_RESET=y, so it's enough to set that.
The Bob board has two USB 3.0 Type-C ports and one USB 2.0 Type-A port
on its right side. Enable the configs relevant to USB devices so these
can be used. This is despite a known issue with RK3399 boards where USB
de-init causes a hang, as there is a known workaround.
Some other rk3399-based devices enable support for the SoC's random
number generator in commit a475bef534 ("configs: rk3399: enable rng on
firefly/rock960/rockpro64"), as it can provide a KASLR seed when booting
using UEFI. Enable it for Bob as well.
The default misc_init_r() for Rockchip boards sets cpuid and ethernet
MAC address based on e-fuse block. A previous patch extends this on Gru
boards to set registers related to SoC IO domains as is necessary on
these boards. Enable this function and configs for it on Bob.
The microSD card slot on this board (and others based on Gru) is
connected to a GPIO controlled regulator (ppvar-sd-card-io), which must
be operable by U-Boot. Enable the relevant config option to allow this.
Bob boards also use the Winbond W25Q64DW SPI flash chip, enable support
for Winbond SPI flash chips in the board config so U-Boot can boot with
this chip.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This adds some devicetree settings for the Gru-based boards, based on
what works on a Kevin board.
Gru-based boards usually have an 8MiB SPI flash chip and boot from it.
Make the u-boot.rom file intended to be flashed on it match its size.
Add properties for booting from SPI, and only try to boot from SPI as
MMC and SD card don't seem to work in SPL yet.
The Chromium OS EC needs a delay between transactions so it can get
itself ready. Also it currently uses a non-standard way of specifying
the interrupt. Add these so that the EC works reliably.
The Rockchip Embedded DisplayPort driver is looking for a rockchip,panel
property to find the panel it should work on. Add the property for the
Gru-based boards.
The U-Boot GPIO controlled regulator driver only considers the
"enable-gpios" devicetree property, not the singular "enable-gpio" one.
Some devicetree source files have the singular form as they were added
to Linux kernel when it used that form, and imported to U-Boot as is.
Fix one instance of this in the Gru boards' devicetree to the form that
works in U-Boot.
The PWM controlled regulator driver complains that there is no init
voltage set for a regulator it drives, though it's not clear which one.
Set them all to the voltage levels coreboot sets them: 900 mV.
The RK3399 SoC needs to know the voltage level that some supplies
provides, including one fixed 1.8V audio-related regulator. Although
this synchronization is currently statically done in the board init
functions, a not-so-hypothetical driver that does this dynamically would
query the regulator only to get -ENODATA and be confused. Make sure
U-Boot knows this supply is at 1.8V by setting its limits to that.
Most of this is a reapplication of commit 08c85b57a5 ("rockchip: gru:
Add extra device-tree settings") whose changes were removed during a
sync with Linux at commit 167efc2c7a ("arm64: dts: rk3399: Sync
v5.7-rc1 from Linux"). Apply things to rk3399-gru-u-boot.dtsi instead so
they don't get lost again.
Signed-off-by: Simon Glass <sjg@chromium.org>
[Alper: move to -u-boot.dtsi, rewrite commit message, add more nodes]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
The RK3399 SoC needs to know the voltage value provided by some
regulators, which is done by setting relevant register bits. Configure
these the way other RK3399 boards do, but with the same values as are
set in the equivalent code in coreboot.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
On RK3568, a register bit must be set to enable Enhanced Strobe.
However, it appears that the address of this register may differ from
vendor to vendor and should be read from the underlying MMC IP. Let the
Rockchip SDHCI driver read this address and set the relevant bit when
Enhanced Strobe configuration is requested.
The IP uses a custom mode select value (0x7) for HS400, use that instead
of the common but non-standard SDHCI_CTRL_HS400 value (0x5). Also add
some necessary DLL_STRBIN and DLL_TXCLK configuration for HS400.
Additionally, a bit signifying that the connected hardware is an eMMC
chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also
make the driver set this bit as appropriate.
This is partly ported from Linux's Synopsys DWC MSHC driver which
happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in
Linux tree).
Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
On RK3399, a register bit must be set to enable Enhanced Strobe.
Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration
is requested. However, having it set makes the lower-speed modes stop
working and makes reinitialization fail, so let it be unset as needed in
set_control_reg().
This is mostly ported from Linux's Arasan SDHCI driver which happens
to be the underlying IP. (drivers/mmc/host/sdhci-of-arasan.c in Linux
tree).
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Delegate setting the Enhanced Strobe configuration to individual drivers
if they set a function for it. Return -ENOTSUPP if they do not, like
what the MMC uclass does.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generic SDHCI driver received support for checking the busy status by
polling the DAT[0] level instead of waiting for the worst MMC switch time.
Unfortunately, it appears that this does not work for Xenon controllers
despite being a part of the standard SDHCI registers and the Armada 3720
datasheet itself telling that BIT(20) is useful for detecting the DAT[0]
busy signal.
I have tried increasing the timeout value, but I have newer managed to
catch DAT_LEVEL bits change from 0 at all.
This issue appears to hit most if not all SoC-s supported by Xenon driver,
at least A3720, A8040 and CN9130 have non working eMMC currently.
So, until a better solution is found drop the wait_dat0 OP for Xenon.
I was able to only test it on A3720, but it should work for others as well.
Fixes: 40e6f52454 ("drivers: mmc: Add wait_dat0 support for sdhci driver")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Stefan Roese <sr@denx.de>
e-MMC and SD standards differ for some CID fields:
- 6 Byte Name - assigned by Manufacturer (SD 5 Byte)
- 1 Byte OEM - assigned by Jedec (SD 2 Byte)
See e-MMC standard (JEDEC Standard No. 84-B51), 7.2.3 (OID) and 7.2.4 (PNM)
Signed-off-by: Max Merchel <Max.Merchel@tq-group.com>
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
After commit f132aab403 ("Revert "mmc: fsl_esdhc_imx: use
VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it
involve issue in mmc_switch_voltage(), because of the special
design of usdhc.
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
these are reserved bits(Though RM contain the definition of these bits,
but actually internal IC logic do not implement, already confirm with
IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card
clock output. Here is the definition of this bit in RM:
[8] FRC_SDCLK_ON
Force CLK output active
Do not set this bit to 1 unless it is necessary. Also, make sure that
this bit is cleared when uSDHC’s clock is about to be changed (frequency
change, clock source change, or delay chain tuning).
0b - CLK active or inactive is fully controlled by the hardware.
1b - Force CLK active
In default, the FRC_SDCLK_ON is 0. This means, when there is no command
or data transfer on bus, hardware will gate off the card clock. But in
some case, we need the card clock keep on. Take IO voltage 1.8v switch
as example, after IO voltage change to 1.8v, spec require gate off the
card clock for 5ms, and gate on the clock back, once detect the card
clock on, then the card will draw the dat0 to high immediately. If there
is not clock gate off/on behavior, some card will keep the dat0 to low
level. This is the reason we fail in mmc_switch_voltage().
To fix this issue, and concern that this is only the fsl usdhc hardware
design limitation, set the bit FRC_SDCLK_ON in the beginning of the
wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage
switch process align with SD specification.
For standard tuning process, usdhc specification also require the card
clock keep on, so also add these behavior in fsl_esdhc_execute_tuning().
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Commit 0934dddc64 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke network on Turris MOX, because the SOC's MDIO bus in
U-Boot currently isn't probed via DM as it's own device, but is
registered as part of mvneta's driver, which means that pinctrl
definitions are not parsed for the MDIO bus node. Also mvneta driver
does not consider "phy-handle" property, only "phy".
For now, fix this by adding armada-3720-turris-mox-u-boot.dtsi file
returning the MDIO to how it was defined previously.
A better solution (using proper mvmdio DM driver) is being work on, but
will need testing on various boards, and we need the bug fixed now for
the upcoming release.
Fixes: 0934dddc64 ("arm: a37xx: Update DTS files to version from upstream Linux kernel")
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
stm32mp1 bsec: Add permanent lock write support
stm32mp1 bsec: Add dev in function description
cmd_stboard: Update test on misc_read() result
video: fix the check of return value of clk_set_rate in stm32_ltdc
DT: Alignment with kernel v5.17 for stm32mp15
DT: Add USB OTG pinctrl and regulator in SPL for DHCOR
DT: Move vdd_io extras into Avenger96 extras
DT: Add DFU support for DHCOM recovery
ram: stm32mp1: Unconditionally enable ASR
psci: Implement PSCI system suspend and DRAM SSR for stm32mp
-----BEGIN PGP SIGNATURE-----
iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmIwUdYcHHBhdHJpY2Uu
Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/pj/FEAClzm1xFrw0oxsIGf9J
Ukyd66yIWiC2rjrxnOh7dtE3toHVVr9+GtM3RohS913BFoVTzlwUlfK75LBrxwWg
Qyp6P8BUWIf8P3Q/x+VcLXuHr/Q+o7prROxclumTEnhzcDhlp/Q6zwXcqXIH77cn
uOxjK5BE1Mt1KI8Fz94EqntoOars5UvxPpye7pahAlGzdZ1PDB1YR8dE5ZjCRG3Q
jNx6I0EZBfjQTHBEtLUSIUGykCDWGJwfbPEgZPa1ePdkgOvDrKQDd0ES89lhjU95
SQG9GFChug+rvXh9i4dxPBK1TGsvCjlZCbrmDGZGLnCfwkHsIzv+ajTpyBzXH5xA
t3XWK0vIaCOpAs1CcRrLjVUA6Paz8qkbTyoGGezvWtRwZ7wV35nI0n/g+R9NM1jC
GR5rrH6yIqrhj6TCneckkIVuiGRRVAXrr43a0BazzzBLSw8N9R8QB8BiM+p4hr8C
anakyfZSN2Y8dBp4EAfzyCV2hOPaUNdaUyzcUIxxDu8eQAqZR0nzjXY6vuV8g702
jr8Q/J2nc520INo6nwHKyOTD4+xAOK81cjQ0LTswTkx67afPmtAXH9EjZLeQ/u9P
ReKCnf/krS/0BhN2WoYXuAl7YQmXyLilrcsA9pXg2fc6lLNw48ZKz0eDZzX549kM
mP8xVQ+qQAiCcIxd+ijwuSSmTA==
=H4+P
-----END PGP SIGNATURE-----
Merge tag 'u-boot-stm32-20220315' of https://source.denx.de/u-boot/custodians/u-boot-stm
mtd: add NAND write protect support to stm32_fmc2_nand
stm32mp1 bsec: Add permanent lock write support
stm32mp1 bsec: Add dev in function description
cmd_stboard: Update test on misc_read() result
video: fix the check of return value of clk_set_rate in stm32_ltdc
DT: Alignment with kernel v5.17 for stm32mp15
DT: Add USB OTG pinctrl and regulator in SPL for DHCOR
DT: Move vdd_io extras into Avenger96 extras
DT: Add DFU support for DHCOM recovery
ram: stm32mp1: Unconditionally enable ASR
psci: Implement PSCI system suspend and DRAM SSR for stm32mp
Using bias-pull-up would actually cause the pin to have its pull-down
enabled. Fix this.
Original Linux patch by Sean Anderson:
https://lore.kernel.org/linux-gpio/20220209182822.640905-1-seanga2@gmail.com/
Fixes: 7224d5ccf8 ("pinctrl: Add support for Kendryte K210 FPIOA")
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
The loop exited too early so the k210_pc_drive_strength[0] array element
was never used.
Original Linux patch by Dan Carpenter:
https://lore.kernel.org/linux-gpio/20220209180804.GA18385@kili/
Fixes: 7224d5ccf8 ("pinctrl: Add support for Kendryte K210 FPIOA")
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
The designware spi driver unconditionally uses polling.
The comment to spi_hw_init() also states that the function should disable
interrupts.
According to the DesignWare DW_apb_ssi Databook, value 0xff in IMR enables
all interrupts. Since we want to mask all interrupts write 0x0 instead.
On the canaan k210 board, pressing the reset button twice to reset the
board will run u-boot. If u-boot boots Linux without having SPI interrupts
masked, Linux will hang as soon as interrupts are enabled, because of an
interrupt storm.
Properly masking the SPI interrupts in u-boot allows us to successfully
boot Linux, even after resetting the board.
Fixes: 5bef6fd79f ("spi: Add designware master SPI DM driver used on SoCFPGA")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
[Niklas: rewrite commit message]
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is documented
to have a 32 word deep TX and RX FIFO, which spi_hw_init() detects.
However, when the RX FIFO is filled up to 32 entries (RXFLR = 32), an
RX FIFO overrun error occurs. Avoid this problem by force setting
fifo_len to 31.
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
