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Merge tag 'u-boot-rockchip-20220318' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

Browse source 
- Fix for chromebook gru and bob board;
- some fix on driver like dram and saradc;
This commit is contained in:
Tom Rini 2022-03-18 16:37:39 -04:00
commit 9776c4e9d0
20 changed files with 308 additions and 8 deletions
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4
MAINTAINERS
View file

@ -397,6 +397,9 @@ M: Philipp Tomsich <philipp.tomsich@vrull.eu>
M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git
F: arch/arm/dts/rk3*
F: arch/arm/dts/rockchip*
F: arch/arm/dts/rv1108*
F: arch/arm/include/asm/arch-rockchip/
F: arch/arm/mach-rockchip/
F: board/rockchip/
@ -414,6 +417,7 @@ F: tools/rkcommon.h
F: tools/rkimage.c
F: tools/rksd.c
F: tools/rkspi.c
N: rockchip
ARM SAMSUNG
M: Minkyu Kang <mk7.kang@samsung.com>

1
arch/arm/dts/Makefile
View file

@ -137,6 +137,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
rk3399-gru-kevin.dtb \
rk3399-khadas-edge.dtb \
rk3399-khadas-edge-captain.dtb \
rk3399-khadas-edge-v.dtb \

11
arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-gru-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
&ppvar_centerlogic_pwm {
regulator-init-microvolt = <925000>;
};

55
arch/arm/dts/rk3399-gru-u-boot.dtsi
View file

@ -5,6 +5,61 @@
#include "rk3399-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = &spi_flash;
};
config {
u-boot,spl-payload-offset = <0x40000>;
};
};
&binman {
rom {
size = <0x800000>;
};
};
&cros_ec {
ec-interrupt = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
};
&edp {
rockchip,panel = <&edp_panel>;
};
&pp1800_audio {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&ppvar_bigcpu_pwm {
regulator-init-microvolt = <900000>;
};
&ppvar_centerlogic_pwm {
regulator-init-microvolt = <900000>;
};
&ppvar_gpu_pwm {
regulator-init-microvolt = <900000>;
};
&ppvar_litcpu_pwm {
regulator-init-microvolt = <900000>;
};
&ppvar_sd_card_io {
enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
};
&spi5 {
spi-activate-delay = <100>;
spi-max-frequency = <3000000>;
spi-deactivate-delay = <200>;
};
&spi_flash {
u-boot,dm-pre-reloc;
};

3
arch/arm/mach-rockchip/Kconfig
View file

@ -390,6 +390,9 @@ config ROCKCHIP_SPI_IMAGE
containing U-Boot. The image is built by binman. U-Boot sits near
the start of the image.
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default SYS_TEXT_BASE
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3128/Kconfig"

11
arch/arm/mach-rockchip/rk3399/Kconfig
View file

@ -14,6 +14,17 @@ config TARGET_CHROMEBOOK_BOB
display. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
config TARGET_CHROMEBOOK_KEVIN
bool "Samsung Chromebook Plus (RK3399)"
select HAS_ROM
select ROCKCHIP_SPI_IMAGE
help
Kevin is a RK3399-based convertible chromebook. It has two USB 3.0
Type-C ports, 4GB of SDRAM, WiFi and a 12.3" 2400x1600 display. It
uses its USB ports for both power and external display. It includes
a Chromium OS EC (Cortex-M3) to provide access to the keyboard and
battery functions.
config TARGET_EVB_RK3399
bool "RK3399 evaluation board"
help

3
arch/arm/mach-rockchip/rk3399/rk3399.c
View file

@ -140,7 +140,8 @@ void board_debug_uart_init(void)
struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB)) {
(IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
rk_setreg(&grf->io_vsel, 1 << 0);
/*

3
arch/arm/mach-rockchip/spl.c
View file

@ -56,7 +56,8 @@ u32 spl_boot_device(void)
defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) || \
defined(CONFIG_TARGET_CHROMEBOOK_BOB)
defined(CONFIG_TARGET_CHROMEBOOK_BOB) || \
defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
return BOOT_DEVICE_SPI;
#endif
if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))

16
board/google/gru/Kconfig
View file

@ -13,3 +13,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
if TARGET_CHROMEBOOK_KEVIN
config SYS_BOARD
default "gru"
config SYS_VENDOR
default "google"
config SYS_CONFIG_NAME
default "gru"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

8
board/google/gru/MAINTAINERS
View file

@ -4,3 +4,11 @@ S: Maintained
F: board/google/gru/
F: include/configs/gru.h
F: configs/chromebook_bob_defconfig
CHROMEBOOK KEVIN BOARD
M: Simon Glass <sjg@chromium.org>
M: Alper Nebi Yasak <alpernebiyasak@gmail.com>
S: Maintained
F: board/google/gru/
F: include/configs/gru.h
F: configs/chromebook_kevin_defconfig

54
board/google/gru/gru.c
View file

@ -6,6 +6,17 @@
#include <common.h>
#include <dm.h>
#include <init.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/misc.h>
#define GRF_IO_VSEL_BT656_SHIFT 0
#define GRF_IO_VSEL_AUDIO_SHIFT 1
#define PMUGRF_CON0_VSEL_SHIFT 8
#define PMUGRF_CON0_VOL_SHIFT 9
#ifdef CONFIG_SPL_BUILD
/* provided to defeat compiler optimisation in board_init_f() */
@ -15,7 +26,7 @@ void gru_dummy_function(int i)
int board_early_init_f(void)
{
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
int sum, i;
/*
@ -54,3 +65,44 @@ int board_early_init_r(void)
return 0;
}
#endif
static void setup_iodomain(void)
{
struct rk3399_grf_regs *grf =
syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
struct rk3399_pmugrf_regs *pmugrf =
syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
/* BT656 and audio is in 1.8v domain */
rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
1 << GRF_IO_VSEL_AUDIO_SHIFT));
/*
* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
* and explicitly configure that PMU1830_VOL to be 1.8V
*/
rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
1 << PMUGRF_CON0_VOL_SHIFT));
}
int misc_init_r(void)
{
const u32 cpuid_offset = 0x7;
const u32 cpuid_length = 0x10;
u8 cpuid[cpuid_length];
int ret;
setup_iodomain();
ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
if (ret)
return ret;
ret = rockchip_cpuid_set(cpuid, cpuid_length);
if (ret)
return ret;
ret = rockchip_setup_macaddr();
return ret;
}

22
configs/chromebook_bob_defconfig
View file

@ -21,6 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x1000
@ -52,8 +53,9 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEYBOARD=y
CONFIG_CROS_EC_KEYB=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
@ -65,13 +67,21 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_CROS_EC=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_DM_RESET=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
@ -80,11 +90,21 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_MAX_XRES=1280
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=800
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y

111
configs/chromebook_kevin_defconfig Normal file
View file

@ -0,0 +1,111 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin"
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
# CONFIG_SPL_MMC is not set
CONFIG_TARGET_CHROMEBOOK_KEVIN=y
CONFIG_DEBUG_UART_BASE=0xff1a0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_HANDOFF=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_LOG=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_CROS_EC_KEYB=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_MMC_PWRSEQ=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_CROS_EC=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_DM_RESET=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_MAX_XRES=2400
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1600
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y

1
configs/roc-cc-rk3328_defconfig
View file

@ -36,6 +36,7 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y

1
doc/board/rockchip/rockchip.rst
View file

@ -66,6 +66,7 @@ List of mainline supported Rockchip boards:
- FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
- FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399)
- Google Bob (chromebook_bob)
- Google Kevin (chromebook_kevin)
- Khadas Edge (khadas-edge-rk3399)
- Khadas Edge-Captain (khadas-edge-captain-rk3399)
- Khadas Edge-V (hadas-edge-v-rk3399)

2
drivers/adc/rockchip-saradc.c
View file

@ -131,7 +131,7 @@ int rockchip_saradc_of_to_plat(struct udevice *dev)
}
priv->data = data;
uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;;
uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;
uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5;
uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;

2
drivers/ram/rockchip/sdram_rk3188.c
View file

@ -762,7 +762,7 @@ static int sdram_init(struct dram_info *dram,
* CS1, n=2
* CS0 & CS1, n = 3
*/
sdram_params->ch[channel].rank = 2,
sdram_params->ch[channel].rank = 2;
clrsetbits_le32(&publ->pgcr, 0xF << 18,
(sdram_params->ch[channel].rank | 1) << 18);

2
drivers/ram/rockchip/sdram_rk3288.c
View file

@ -862,7 +862,7 @@ static int sdram_init(struct dram_info *dram,
* CS1, n=2
* CS0 & CS1, n = 3
*/
sdram_params->ch[channel].rank = 2,
sdram_params->ch[channel].rank = 2;
clrsetbits_le32(&publ->pgcr, 0xF << 18,
(sdram_params->ch[channel].rank | 1) << 18);

3
include/configs/gru.h
View file

@ -13,4 +13,7 @@
#include <configs/rk3399_common.h>
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#endif

3
include/dt-bindings/input/linux-event-codes.h
View file

@ -749,7 +749,8 @@
#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */
#define SW_LINEIN_INSERT 0x0d /* set = inserted */
#define SW_MUTE_DEVICE 0x0e /* set = device disabled */
#define SW_MAX 0x0f
#define SW_PEN_INSERTED 0x0f /* set = pen inserted */
#define SW_MAX 0x10
#define SW_CNT (SW_MAX+1)
/*