Enables SPL NAND support for ARCH_K3 by enabling
SPL_NAND_INIT and SPL_SYS_NAND_SELF_INIT.
Legacy OMAP2plus platforms still rely on SPL_NAND_AM33XX_BCH
instead.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221220102203.52398-6-rogerq@kernel.org
Upstream linux commit 3b5206f4be9b65.
Move Macronix specific initialization logic into nand_macronix.c. This
is part of the "separate vendor specific code from core" cleanup
process.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Upstream linux commit 229204da53b31d.
Move AMD/Spansion specific initialization/detection logic into
nand_amd.c. This is part of the "separate vendor specific code from
core" cleanup process.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Upstream linux commit 10d4e75c36f6c1.
Move Micron specific initialization logic into nand_micron.c. This is
part of the "separate vendor specific code from core" cleanup process.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Upstream linux commit 9b2d61f80b060c.
Move Toshiba specific initialization and detection logic into
nand_toshiba.c. This is part of the "separate vendor specific code from
core" cleanup process.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Upstream linux commit 01389b6bd2f4f7.
Move Hynix specific initialization and detection logic into
nand_hynix.c. This is part of the "separate vendor specific code from
core" cleanup process.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Upstream linux commit c51d0ac59f2420.
Move Samsung specific initialization and detection logic into
nand_samsung.c. This is part of the "separate vendor specific code from
core" cleanup process.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
This patch adds NAND flash controller driver for MediaTek MT7621 SoC.
The NAND flash controller of MT7621 supports only SLC NAND flashes.
It supports 4~12 bits correction with maximum 4KB page size.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Add a driver for Macronix raw NAND controller.
This patch referred from linux mxic_nand.c. The difference from the
linux version is described here.
1. In order to adapt to the uboot nand framework, add function
binding (cmdfunc, read_byte, read_buf, write_buf).
2. Added parsing command format to use hardware correctly.
3. Remove the incompatible functions of Uboot.
Signed-off-by: Zhengxun Li <zhengxunli@mxic.com.tw>
This driver supports Rockchip NFC (NAND Flash Controller) found on
RK3308, RK2928, RKPX30, RV1108 and other SOCs. The driver has been
tested using 8-bit NAND interface on the ARM based RK3308 platform.
Support Rockchip SoCs and NFC versions:
- PX30 and RK3326(NFCv900).
ECC: 16/40/60/70 bits/1KB.
CLOCK: ahb and nfc.
- RK3308 and RV1108(NFCv800).
ECC: 16 bits/1KB.
CLOCK: ahb and nfc.
- RK3036 and RK3128(NFCv622).
ECC: 16/24/40/60 bits/1KB.
CLOCK: ahb and nfc.
- RK3066, RK3188 and RK2928(NFCv600).
ECC: 16/24/40/60 bits/1KB.
CLOCK: ahb.
Supported features:
- Read full page data by DMA.
- Support HW ECC(one step is 1KB).
- Support 2 - 32K page size.
- Support 8 CS(depend on SoCs)
Limitations:
- No support for the ecc step size is 512.
- Untested on some SoCs.
- No support for subpages.
- No support for the builtin randomizer.
- The original bad block mask is not supported. It is recommended to
use the BBT(bad block table).
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Cortina Access parallel Nand support for CAxxxx SOCs
Signed-off-by: Kate Liu <kate.liu@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
CC: Scott Wood <oss@buserror.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds support for NAND controllers found on OcteonTX or
OcteonTX2 SoC platforms. Also includes driver to support
Hardware ECC using BCH HW engine found on these platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The driver brcmnand come from linux kernel 4.18.
Only SoC bcm6838 and bcm6858 are supported.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.
This patch adds the polling mode, a basic mode that do not need
any DMA channels.
Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC
based on Hamming)
This patch has been tested on Micron MT29F8G08ABACAH4.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
NAND flavors, like serial and parallel, have a lot in common and would
benefit to share code. Let's move raw (parallel) NAND specific code in a
raw/ subdirectory, to ease the addition of a core file in nand/ and the
introduction of a spi/ subdirectory specific to SPI NANDs.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
