mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 23:51:33 +00:00
mtd: rawnand: Add Macronix raw NAND controller driver
Add a driver for Macronix raw NAND controller. This patch referred from linux mxic_nand.c. The difference from the linux version is described here. 1. In order to adapt to the uboot nand framework, add function binding (cmdfunc, read_byte, read_buf, write_buf). 2. Added parsing command format to use hardware correctly. 3. Remove the incompatible functions of Uboot. Signed-off-by: Zhengxun Li <zhengxunli@mxic.com.tw>
This commit is contained in:
Zhengxun Li
Tom Rini
parent
5f9338ad56
commit
0892a7e5fa
3 changed files with 610 additions and 0 deletions
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@ -398,6 +398,12 @@ config NAND_MXS_USE_MINIMUM_ECC
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endif
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config NAND_MXIC
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bool "Macronix raw NAND controller"
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select SYS_NAND_SELF_INIT
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help
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This selects the Macronix raw NAND controller driver.
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config NAND_ZYNQ
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bool "Support for Zynq Nand controller"
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select SYS_NAND_SELF_INIT
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@ -67,6 +67,7 @@ obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
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obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
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obj-$(CONFIG_NAND_PLAT) += nand_plat.o
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obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
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obj-$(CONFIG_NAND_MXIC) += mxic_nand.o
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obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
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obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
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obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
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603
drivers/mtd/nand/raw/mxic_nand.c
Normal file
603
drivers/mtd/nand/raw/mxic_nand.c
Normal file
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@ -0,0 +1,603 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Macronix International Co., Ltd.
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*
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* Author:
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* Zhengxun Li <zhengxunli@mxic.com.tw>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <malloc.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <dm/device_compat.h>
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#include <linux/bug.h>
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#include <linux/errno.h>
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#include <linux/iopoll.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/delay.h>
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#define HC_CFG 0x0
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#define HC_CFG_IF_CFG(x) ((x) << 27)
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#define HC_CFG_DUAL_SLAVE BIT(31)
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#define HC_CFG_INDIVIDUAL BIT(30)
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#define HC_CFG_NIO(x) (((x) / 4) << 27)
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#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
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#define HC_CFG_TYPE_SPI_NOR 0
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#define HC_CFG_TYPE_SPI_NAND 1
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#define HC_CFG_TYPE_SPI_RAM 2
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#define HC_CFG_TYPE_RAW_NAND 3
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#define HC_CFG_SLV_ACT(x) ((x) << 21)
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#define HC_CFG_CLK_PH_EN BIT(20)
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#define HC_CFG_CLK_POL_INV BIT(19)
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#define HC_CFG_BIG_ENDIAN BIT(18)
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#define HC_CFG_DATA_PASS BIT(17)
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#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
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#define HC_CFG_MAN_START_EN BIT(3)
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#define HC_CFG_MAN_START BIT(2)
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#define HC_CFG_MAN_CS_EN BIT(1)
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#define HC_CFG_MAN_CS_ASSERT BIT(0)
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#define INT_STS 0x4
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#define INT_STS_EN 0x8
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#define INT_SIG_EN 0xc
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#define INT_STS_ALL GENMASK(31, 0)
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#define INT_RDY_PIN BIT(26)
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#define INT_RDY_SR BIT(25)
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#define INT_LNR_SUSP BIT(24)
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#define INT_ECC_ERR BIT(17)
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#define INT_CRC_ERR BIT(16)
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#define INT_LWR_DIS BIT(12)
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#define INT_LRD_DIS BIT(11)
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#define INT_SDMA_INT BIT(10)
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#define INT_DMA_FINISH BIT(9)
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#define INT_RX_NOT_FULL BIT(3)
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#define INT_RX_NOT_EMPTY BIT(2)
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#define INT_TX_NOT_FULL BIT(1)
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#define INT_TX_EMPTY BIT(0)
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#define HC_EN 0x10
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#define HC_EN_BIT BIT(0)
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#define TXD(x) (0x14 + ((x) * 4))
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#define RXD 0x24
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#define SS_CTRL(s) (0x30 + ((s) * 4))
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#define LRD_CFG 0x44
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#define LWR_CFG 0x80
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#define RWW_CFG 0x70
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#define OP_READ BIT(23)
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#define OP_DUMMY_CYC(x) ((x) << 17)
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#define OP_ADDR_BYTES(x) ((x) << 14)
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#define OP_CMD_BYTES(x) (((x) - 1) << 13)
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#define OP_OCTA_CRC_EN BIT(12)
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#define OP_DQS_EN BIT(11)
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#define OP_ENHC_EN BIT(10)
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#define OP_PREAMBLE_EN BIT(9)
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#define OP_DATA_DDR BIT(8)
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#define OP_DATA_BUSW(x) ((x) << 6)
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#define OP_ADDR_DDR BIT(5)
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#define OP_ADDR_BUSW(x) ((x) << 3)
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#define OP_CMD_DDR BIT(2)
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#define OP_CMD_BUSW(x) (x)
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#define OP_BUSW_1 0
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#define OP_BUSW_2 1
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#define OP_BUSW_4 2
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#define OP_BUSW_8 3
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#define OCTA_CRC 0x38
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#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
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#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
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#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
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#define ONFI_DIN_CNT(s) (0x3c + (s))
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#define LRD_CTRL 0x48
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#define RWW_CTRL 0x74
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#define LWR_CTRL 0x84
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#define LMODE_EN BIT(31)
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#define LMODE_SLV_ACT(x) ((x) << 21)
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#define LMODE_CMD1(x) ((x) << 8)
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#define LMODE_CMD0(x) (x)
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#define LRD_ADDR 0x4c
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#define LWR_ADDR 0x88
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#define LRD_RANGE 0x50
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#define LWR_RANGE 0x8c
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#define AXI_SLV_ADDR 0x54
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#define DMAC_RD_CFG 0x58
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#define DMAC_WR_CFG 0x94
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#define DMAC_CFG_PERIPH_EN BIT(31)
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#define DMAC_CFG_ALLFLUSH_EN BIT(30)
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#define DMAC_CFG_LASTFLUSH_EN BIT(29)
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#define DMAC_CFG_QE(x) (((x) + 1) << 16)
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#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
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#define DMAC_CFG_BURST_SZ(x) ((x) << 8)
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#define DMAC_CFG_DIR_READ BIT(1)
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#define DMAC_CFG_START BIT(0)
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#define DMAC_RD_CNT 0x5c
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#define DMAC_WR_CNT 0x98
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#define SDMA_ADDR 0x60
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#define DMAM_CFG 0x64
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#define DMAM_CFG_START BIT(31)
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#define DMAM_CFG_CONT BIT(30)
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#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
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#define DMAM_CFG_DIR_READ BIT(1)
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#define DMAM_CFG_EN BIT(0)
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#define DMAM_CNT 0x68
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#define LNR_TIMER_TH 0x6c
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#define RDM_CFG0 0x78
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#define RDM_CFG0_POLY(x) (x)
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#define RDM_CFG1 0x7c
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#define RDM_CFG1_RDM_EN BIT(31)
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#define RDM_CFG1_SEED(x) (x)
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#define LWR_SUSP_CTRL 0x90
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#define LWR_SUSP_CTRL_EN BIT(31)
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#define DMAS_CTRL 0x9c
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#define DMAS_CTRL_EN BIT(31)
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#define DMAS_CTRL_DIR_READ BIT(30)
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#define DATA_STROB 0xa0
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#define DATA_STROB_EDO_EN BIT(2)
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#define DATA_STROB_INV_POL BIT(1)
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#define DATA_STROB_DELAY_2CYC BIT(0)
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#define IDLY_CODE(x) (0xa4 + ((x) * 4))
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#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
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#define GPIO 0xc4
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#define GPIO_PT(x) BIT(3 + ((x) * 16))
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#define GPIO_RESET(x) BIT(2 + ((x) * 16))
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#define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
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#define GPIO_WPB(x) BIT((x) * 16)
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#define HC_VER 0xd0
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#define HW_TEST(x) (0xe0 + ((x) * 4))
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#define MXIC_NFC_MAX_CLK_HZ 50000000
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#define IRQ_TIMEOUT 1000
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struct mxic_nand_ctrl {
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struct clk *send_clk;
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struct clk *send_dly_clk;
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void __iomem *regs;
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struct nand_chip nand_chip;
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};
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/*
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* struct mxic_nfc_command_format - Defines NAND flash command format
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* @start_cmd: First cycle command (Start command)
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* @end_cmd: Second cycle command (Last command)
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* @addr_len: Number of address cycles required to send the address
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* @read: Direction of command
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*/
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struct mxic_nfc_command_format {
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int start_cmd;
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int end_cmd;
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u8 addr_len;
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bool read;
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};
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/* The NAND flash operations command format */
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static const struct mxic_nfc_command_format mxic_nand_commands[] = {
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{NAND_CMD_READ0, NAND_CMD_READSTART, 5, 1 },
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{NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, 1 },
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{NAND_CMD_READID, NAND_CMD_NONE, 1, 1 },
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{NAND_CMD_STATUS, NAND_CMD_NONE, 0, 1 },
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{NAND_CMD_SEQIN, NAND_CMD_NONE, 5, 0 },
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{NAND_CMD_PAGEPROG, NAND_CMD_NONE, 0, 0 },
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{NAND_CMD_CACHEDPROG, NAND_CMD_NONE, 0, 0 },
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{NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0 },
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{NAND_CMD_ERASE1, NAND_CMD_NONE, 3, 0 },
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{NAND_CMD_ERASE2, NAND_CMD_NONE, 0, 0 },
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{NAND_CMD_RESET, NAND_CMD_NONE, 0, 0 },
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{NAND_CMD_PARAM, NAND_CMD_NONE, 1, 1 },
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{NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 1 },
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{NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0 },
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{NAND_CMD_NONE, NAND_CMD_NONE, 0, 0 },
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};
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static int mxic_nfc_clk_enable(struct mxic_nand_ctrl *nfc)
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{
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int ret;
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ret = clk_prepare_enable(nfc->send_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(nfc->send_dly_clk);
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if (ret)
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goto err_send_dly_clk;
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return ret;
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err_send_dly_clk:
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clk_disable_unprepare(nfc->send_clk);
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return ret;
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}
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static void mxic_nfc_clk_disable(struct mxic_nand_ctrl *nfc)
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{
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clk_disable_unprepare(nfc->send_clk);
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clk_disable_unprepare(nfc->send_dly_clk);
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}
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static void mxic_nfc_set_input_delay(struct mxic_nand_ctrl *nfc, u8 idly_code)
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{
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writel(IDLY_CODE_VAL(0, idly_code) |
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IDLY_CODE_VAL(1, idly_code) |
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IDLY_CODE_VAL(2, idly_code) |
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IDLY_CODE_VAL(3, idly_code),
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nfc->regs + IDLY_CODE(0));
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writel(IDLY_CODE_VAL(4, idly_code) |
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IDLY_CODE_VAL(5, idly_code) |
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IDLY_CODE_VAL(6, idly_code) |
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IDLY_CODE_VAL(7, idly_code),
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nfc->regs + IDLY_CODE(1));
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}
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static int mxic_nfc_clk_setup(struct mxic_nand_ctrl *nfc, unsigned long freq)
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{
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int ret;
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ret = clk_set_rate(nfc->send_clk, freq);
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if (ret)
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return ret;
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ret = clk_set_rate(nfc->send_dly_clk, freq);
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if (ret)
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return ret;
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/*
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* A constant delay range from 0x0 ~ 0x1F for input delay,
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* the unit is 78 ps, the max input delay is 2.418 ns.
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*/
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mxic_nfc_set_input_delay(nfc, 0xf);
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return 0;
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}
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static int mxic_nfc_set_freq(struct mxic_nand_ctrl *nfc, unsigned long freq)
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{
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int ret;
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if (freq > MXIC_NFC_MAX_CLK_HZ)
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freq = MXIC_NFC_MAX_CLK_HZ;
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mxic_nfc_clk_disable(nfc);
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ret = mxic_nfc_clk_setup(nfc, freq);
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if (ret)
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return ret;
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ret = mxic_nfc_clk_enable(nfc);
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if (ret)
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return ret;
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return 0;
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}
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static void mxic_nfc_hw_init(struct mxic_nand_ctrl *nfc)
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{
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writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) |
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HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN |
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HC_CFG_IDLE_SIO_LVL(1), nfc->regs + HC_CFG);
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writel(INT_STS_ALL, nfc->regs + INT_STS_EN);
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writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN);
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writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
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writel(0, nfc->regs + LRD_CFG);
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writel(0, nfc->regs + LRD_CTRL);
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writel(0x0, nfc->regs + HC_EN);
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}
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static void mxic_nfc_cs_enable(struct mxic_nand_ctrl *nfc)
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{
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writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
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nfc->regs + HC_CFG);
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writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG),
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nfc->regs + HC_CFG);
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}
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static void mxic_nfc_cs_disable(struct mxic_nand_ctrl *nfc)
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{
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writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG),
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nfc->regs + HC_CFG);
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}
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static int mxic_nfc_data_xfer(struct mxic_nand_ctrl *nfc, const void *txbuf,
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void *rxbuf, unsigned int len)
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{
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unsigned int pos = 0;
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while (pos < len) {
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unsigned int nbytes = len - pos;
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u32 data = 0xffffffff;
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u32 sts;
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int ret;
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if (nbytes > 4)
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nbytes = 4;
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if (txbuf)
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memcpy(&data, txbuf + pos, nbytes);
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ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
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sts & INT_TX_EMPTY, 1000000);
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if (ret)
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return ret;
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writel(data, nfc->regs + TXD(nbytes % 4));
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ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
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sts & INT_TX_EMPTY, 1000000);
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if (ret)
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return ret;
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ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
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sts & INT_RX_NOT_EMPTY, 1000000);
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if (ret)
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return ret;
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data = readl(nfc->regs + RXD);
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if (rxbuf) {
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data >>= (8 * (4 - nbytes));
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memcpy(rxbuf + pos, &data, nbytes);
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}
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WARN_ON(readl(nfc->regs + INT_STS) & INT_RX_NOT_EMPTY);
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pos += nbytes;
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}
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return 0;
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}
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static uint8_t mxic_nfc_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
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u8 data;
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writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
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writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
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OP_READ, nfc->regs + SS_CTRL(0));
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mxic_nfc_data_xfer(nfc, NULL, &data, 1);
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return data;
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}
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static void mxic_nfc_read_buf(struct mtd_info *mtd, uint8_t *rxbuf, int rlen)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
|
||||
|
||||
writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
|
||||
writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
|
||||
OP_READ, nfc->regs + SS_CTRL(0));
|
||||
|
||||
mxic_nfc_data_xfer(nfc, NULL, rxbuf, rlen);
|
||||
}
|
||||
|
||||
static void mxic_nfc_write_buf(struct mtd_info *mtd, const uint8_t *txbuf,
|
||||
int wlen)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
|
||||
|
||||
writel(wlen, nfc->regs + ONFI_DIN_CNT(0));
|
||||
writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F),
|
||||
nfc->regs + SS_CTRL(0));
|
||||
|
||||
mxic_nfc_data_xfer(nfc, txbuf, NULL, wlen);
|
||||
}
|
||||
|
||||
static void mxic_nfc_cmd_function(struct mtd_info *mtd, unsigned int command,
|
||||
int column, int page_addr)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
|
||||
const struct mxic_nfc_command_format *cmd = NULL;
|
||||
u32 sts;
|
||||
u8 index, addr[5];
|
||||
|
||||
/* Emulate NAND_CMD_READOOB */
|
||||
if (command == NAND_CMD_READOOB) {
|
||||
column += mtd->writesize;
|
||||
command = NAND_CMD_READ0;
|
||||
}
|
||||
|
||||
/* Get the command format */
|
||||
for (index = 0; index < ARRAY_SIZE(mxic_nand_commands); index++)
|
||||
if (command == mxic_nand_commands[index].start_cmd)
|
||||
break;
|
||||
|
||||
cmd = &mxic_nand_commands[index];
|
||||
|
||||
if (!(command == NAND_CMD_PAGEPROG ||
|
||||
command == NAND_CMD_CACHEDPROG ||
|
||||
command == NAND_CMD_ERASE2))
|
||||
mxic_nfc_cs_disable(nfc);
|
||||
|
||||
mxic_nfc_cs_enable(nfc);
|
||||
|
||||
if (column != -1) {
|
||||
addr[0] = column;
|
||||
addr[1] = column >> 8;
|
||||
|
||||
if (page_addr != -1) {
|
||||
addr[2] = page_addr;
|
||||
addr[3] = page_addr >> 8;
|
||||
addr[4] = page_addr >> 16;
|
||||
}
|
||||
} else if (page_addr != -1) {
|
||||
addr[0] = page_addr;
|
||||
addr[1] = page_addr >> 8;
|
||||
addr[2] = page_addr >> 16;
|
||||
}
|
||||
|
||||
writel(0, nfc->regs + HC_EN);
|
||||
writel(HC_EN_BIT, nfc->regs + HC_EN);
|
||||
writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | OP_CMD_BYTES(0),
|
||||
nfc->regs + SS_CTRL(0));
|
||||
|
||||
mxic_nfc_data_xfer(nfc, &cmd->start_cmd, NULL, 1);
|
||||
|
||||
if (cmd->addr_len) {
|
||||
writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
|
||||
OP_ADDR_BYTES(cmd->addr_len), nfc->regs + SS_CTRL(0));
|
||||
|
||||
mxic_nfc_data_xfer(nfc, &addr, NULL, cmd->addr_len);
|
||||
}
|
||||
|
||||
if (cmd->end_cmd != NAND_CMD_NONE) {
|
||||
writel(0, nfc->regs + HC_EN);
|
||||
writel(HC_EN_BIT, nfc->regs + HC_EN);
|
||||
writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
|
||||
OP_CMD_BYTES(0), nfc->regs + SS_CTRL(0));
|
||||
|
||||
mxic_nfc_data_xfer(nfc, &cmd->end_cmd, NULL, 1);
|
||||
}
|
||||
|
||||
readl_poll_timeout(nfc->regs + INT_STS, sts, sts & INT_RDY_PIN,
|
||||
1000000);
|
||||
|
||||
if (command == NAND_CMD_PAGEPROG ||
|
||||
command == NAND_CMD_CACHEDPROG ||
|
||||
command == NAND_CMD_ERASE2 ||
|
||||
command == NAND_CMD_RESET) {
|
||||
mxic_nfc_cs_disable(nfc);
|
||||
}
|
||||
}
|
||||
|
||||
static int mxic_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr,
|
||||
const struct nand_data_interface *conf)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
|
||||
const struct nand_sdr_timings *sdr;
|
||||
unsigned long freq;
|
||||
int ret;
|
||||
|
||||
sdr = nand_get_sdr_timings(conf);
|
||||
if (IS_ERR(sdr))
|
||||
return PTR_ERR(sdr);
|
||||
|
||||
if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
|
||||
return 0;
|
||||
|
||||
freq = 1000000000 / (sdr->tRC_min / 1000);
|
||||
|
||||
ret = mxic_nfc_set_freq(nfc, freq);
|
||||
if (ret)
|
||||
WARN_ON("Set freq failed\n");
|
||||
|
||||
if (sdr->tRC_min < 30000)
|
||||
writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Dummy implementation: we don't support multiple chips */
|
||||
static void mxic_nfc_select_chip(struct mtd_info *mtd, int chipnr)
|
||||
{
|
||||
switch (chipnr) {
|
||||
case -1:
|
||||
case 0:
|
||||
break;
|
||||
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static int mxic_nfc_probe(struct udevice *dev)
|
||||
{
|
||||
struct mxic_nand_ctrl *nfc = dev_get_priv(dev);
|
||||
struct nand_chip *nand_chip = &nfc->nand_chip;
|
||||
struct mtd_info *mtd;
|
||||
ofnode child;
|
||||
int err;
|
||||
|
||||
nfc->regs = (void *)dev_read_addr(dev);
|
||||
|
||||
nfc->send_clk = devm_clk_get(dev, "send");
|
||||
if (IS_ERR(nfc->send_clk))
|
||||
return PTR_ERR(nfc->send_clk);
|
||||
|
||||
nfc->send_dly_clk = devm_clk_get(dev, "send_dly");
|
||||
if (IS_ERR(nfc->send_dly_clk))
|
||||
return PTR_ERR(nfc->send_dly_clk);
|
||||
|
||||
mtd = nand_to_mtd(nand_chip);
|
||||
|
||||
ofnode_for_each_subnode(child, dev_ofnode(dev))
|
||||
nand_set_flash_node(nand_chip, child);
|
||||
|
||||
nand_set_controller_data(nand_chip, nfc);
|
||||
|
||||
nand_chip->select_chip = mxic_nfc_select_chip;
|
||||
nand_chip->setup_data_interface = mxic_nfc_setup_data_interface;
|
||||
nand_chip->cmdfunc = mxic_nfc_cmd_function;
|
||||
nand_chip->read_byte = mxic_nfc_read_byte;
|
||||
nand_chip->read_buf = mxic_nfc_read_buf;
|
||||
nand_chip->write_buf = mxic_nfc_write_buf;
|
||||
|
||||
mxic_nfc_hw_init(nfc);
|
||||
|
||||
err = nand_scan(mtd, 1);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = nand_register(0, mtd);
|
||||
if (err) {
|
||||
dev_err(dev, "Failed to register MTD: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id mxic_nfc_of_ids[] = {
|
||||
{ .compatible = "mxic,multi-itfc-v009-nand-controller" },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mxic_nfc) = {
|
||||
.name = "mxic_nfc",
|
||||
.id = UCLASS_MTD,
|
||||
.of_match = mxic_nfc_of_ids,
|
||||
.probe = mxic_nfc_probe,
|
||||
.priv_auto = sizeof(struct mxic_nand_ctrl),
|
||||
};
|
||||
|
||||
void board_nand_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MTD,
|
||||
DM_DRIVER_GET(mxic_nfc), &dev);
|
||||
if (ret && ret != -ENODEV)
|
||||
pr_err("Failed to initialize %s. (error %d)\n", dev->name,
|
||||
ret);
|
||||
}
|
||||
Loading…
Reference in a new issue