Commit graph

15 commits

Author SHA1 Message Date
Patrick Delaunay
f050e3fe45 arm: dts: stm32mp15: alignment with v5.11-rc2
Device tree alignment with Linux kernel v5.11-rc2
- fix DCMI DMA features on stm32mp15 family
- Add alternate pinmux for FMC EBI bus
- Harmonize EHCI/OHCI DT nodes name on stm32mp15
- update sdmmc IP version for STM32MP15
- Add LP timer irqs on stm32mp151
- Add LP timer wakeup-source on stm32mp151
- enable HASH by default on stm32mp15
- enable CRC1 by default on stm32mp15
- enable CRYP by default on stm32mp15
- set bus-type in DCMI endpoint for stm32mp157c-ev1 board
- reorder spi4 within stm32mp15-pinctrl
- add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx
- fix mdma1 clients channel priority level on stm32mp151
- fix dmamux reg property on stm32mp151
- adjust USB OTG gadget fifo sizes in stm32mp151
- update stm32mp151 for remote proc synchronization support
- support child mfd cells for the stm32mp1 TAMP syscon

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-09 10:56:06 +01:00
Marek Vasut
69ea30e688 ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock
The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P.
To permit PLL4P to run at faster frequency, use MCO2 as a divider.
The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to
50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback
clock are fed back in via pin PA1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ia9bf7119785d49b633a3ae761c3dc4a30b92628a
2021-01-13 09:52:58 +01:00
Marek Vasut
9ff770b497 ARM: dts: stm32: Update eth1addr from EEPROM if eth1 present
The STM32MP1 DHCOM has two ethernet interfaces, the on-SoM DWMAC and KS8851.
Set eth1addr for the KS8851 to a MAC address of the DWMAC incremented by 1.
The MAC of the DWMAC is set from on-SoM EEPROM already, but the MAC address
of KS8851 was left uninitialized, so fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-08-13 09:56:44 +02:00
Patrick Delaunay
ed111e4f00 Revert "ARM: dts: stm32: Reinstate card detect behavior on DHSOM"
Since commit f13ff88b61 ("gpio: stm32: add ops set_dir_flags")
the gpio flags are supported by stm32 pinctrl driver.

The cd-gpios is correctly handle in U-Boot and the patch on the
device tree can be removed.

This reverts commit 3c2e2a1a79.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 18:14:58 +02:00
Patrick Delaunay
4a87fea6de ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL
This patch allows to switch the CPU frequency to 800MHz on the
ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM
using the STM32MP15x SOC and when it is supported by the HW
(for STM32MP15xD and STM32MP15xF).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Marek Vasut
3c2e2a1a79 ARM: dts: stm32: Reinstate card detect behavior on DHSOM
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This permits the DHSOM to boot from SD again,
without this patch the card detect fails.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-19 09:43:59 +02:00
Marek Vasut
1e444bdc98 ARM: stm32: Hog GPIO PF7 high on DHCOM to unlock SPI NOR nWP
The SPI NOR nWP line is connected to GPIO PF7 on the SoM,
pull the GPIO line high by default to clear SPI NOR WP.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Marek Vasut
92ca0f7446 ARM: dts: stm32: Synchronize DDR setttings on DH SoMs
Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them
into use by the board file instead of the default ones. These new DRAM
settings are a better fit for the SoMs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Marek Vasut
2d68365da1 ARM: stm32: Implement DDR3 coding on DHCOR SoM
The DHCOR board does exist in multiple variants with different DDR3
DRAM sizes. To cater for all of them, implement DDR3 code handling.
There are two GPIOs which code the DRAM size populated on the SoM,
read them out and use the value to pick the correct DDR3 config.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Marek Vasut
731fd50e27 ARM: stm32: Implement board coding on AV96
The AV96 board does exist in multiple variants. To cater for all of
them, implement board code handling. There are two GPIOs which code
the type of the board, read them out and use the value to pick the
correct device tree from an fitImage.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: Iddb330b9a66500495885457cbe17edc0eacaaf43
2020-05-14 09:02:12 +02:00
Marek Vasut
de80a2476a ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2
Add DT entries, Kconfig entries and board-specific entries to configure
FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-15 09:08:29 +02:00
Patrick Delaunay
1a4f57c895 ARM: dts: stm32mp1: DT alignment with Linux 5.6-rc1
This commit manages diversity for STM32M15x SOCs with:
- dedicated files to support all STM32MP15 SOCs family.
  The differences between those SOCs are:
  -STM32MP151 [1]: common file.
  -STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU.
  -STM32MP157 [3]: STM32MP153 + DSI + GPU.
- new files to manage security diversity on STM32MP15x SOCs.
  On STM32MP15xY, "Y" gives information:
  -Y = A means no cryp IP and no secure boot.
  -Y = C means cryp IP + secure boot.
- stm32mp157 pinctrl files to better manage package diversity.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:18:36 +01:00
Patrick Delaunay
8d93a9755f ARM: dts: stm32m1: add reg for pll nodes
Fix the following DT dtc warnings for stm32mp1 boards:

Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@0:
  node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@1:
  node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@2:
  node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@3:
  node has a unit name, but no reg property

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-02-13 17:26:23 +01:00
Antonio Borneo
db0cd2d3bc ARM: dts: stm32mp1: move FDCAN to PLL4_R
LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
cache the value at probe and pretend to use it later.

Keep the LTDC alone on PLL4_Q by moving the FDCAN to PLL4_R.

Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-02-13 17:26:22 +01:00
Marek Vasut
199537309b ARM: dts: stm32: Add DH Electronics DHCOM SoM and PDK2 board
Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier
board. This is an SoM with STM32MP15xx and an evaluation kit. The
baseboard provides Ethernet, UART, USB, CAN and optional display.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-02-12 19:48:39 +01:00