Commit graph

17 commits

Author SHA1 Message Date
Kumar Gala
7dc358bb0d 85xx: Get ride of old TLB setup code
Now that all boards have been converted, remove old config code and the
config option for the new style.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:19:18 -06:00
Kumar Gala
8716318057 85xx: Reworked initial processor init
Reworked the initial processor initialzation sequence:
* introduced cpu_early_init_f that is run in address space 1 (AS=1)
* Moved TLB/LAW and CCSR init into cpu_early_init_f()
* Reworked initial asm code to do most of the core init before TLBs

The main reasons for these changes are to allow handling of 36-bit phys
addresses in the future and some of the issues that will exist when we
do that.

There are a few caveats on what can be initialized via the LAW and TLB
static tables:
* TLB entry 14/15 can't be initialized via the TLB table
* any LAW that covers the implicit boot window (4G-8M to 4G) must map to
  the code that is currently executing.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:04:53 -06:00
Kumar Gala
83d40dfd79 85xx: Move LAW init code into C
Move the initialization of the LAWs into C code and provide an API
to allow modification of LAWs after init.

Board code is responsible to provide a law_table and num_law_entries.

We should be able to use the same code on 86xx as well.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-16 23:21:55 -06:00
Kumar Gala
04db400892 Stop using immap_t on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Kumar Gala
aafeefbdb8 Stop using immap_t for cpm offset on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers
instead of getting it via &immap->im_cpm.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:19 -06:00
Haiying Wang
7a1ac419fa Enable L2 cache for MPC8568MDS board
The L2 cache size is 512KB for 8568, print out the correct informaiton.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2007-08-29 00:11:44 -05:00
Andy Fleming
da9d4610d7 Add support for UEC to 8568
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:47:44 -05:00
Andy Fleming
6c543597bb Fix minor 85xx warnings
Some patches had inserted warnings into the build:
* mpc8560ads declared data without using it
* cpu_init declared ecm and immap without using it in all CONFIGs
* MPC8548CDS.h had its default filenames changed so that they contained
  "\m" in the paths.  Made the defaults not Windows-specific (or
  anything-specific)

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:39:14 -05:00
Ed Swarthout
29372ff38c mpc85xx L2 cache reporting and SRAM relocation option.
Allow debugger to override flash cs0/cs1 settings to enable alternate
boot regions

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:21:55 -05:00
Andy Fleming
6743105988 Add support for the 8568 MDS board
This included some changes to common files:
* Add 8568 processor SVR to various places
* Add support for setting the qe bus-frequency value in the dts
* Add the 8568MDS target to the Makefile

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-05-02 15:50:02 -05:00
Matthew McClintock
40d5fa35d0 * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards
Patch by Jon Loeliger 17-Jan-2006

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-06-28 10:43:36 -05:00
Wolfgang Denk
d87080b721 GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31 18:32:53 +02:00
Jon Loeliger
d9b94f28a4 * Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
  Added DDR II support based on SPD values for MPC85xx boards.
  This roll-up patch also includes bugfies for the previously
  published patches:
    DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
2005-07-25 14:05:07 -05:00
Jon Loeliger
d65cfe89ec * Patch by Jon Loeliger 2005-02-08
Determine L2 Cache size dynamically on 85XX boards.
2005-07-25 10:58:39 -05:00
Jon Loeliger
9c4c5ae3e1 * Patch by Jon Loeliger, Kumar Gala 2005-02-08
- Convert the CPM2 based functionality to use new CONFIG_CPM2
    option rather than a myriad of CONFIG_MPC8560-like variants.
    Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
    Eliminates the CONFIG_MPC8560 option entirely.  Distributes the
    new CONFIG_CPM2 option to each 8260 board.
2005-07-23 10:37:35 -05:00
wdenk
6c9e789e9e Update code for TQM8540 board (and 85xx in general):
- Change the name of the Ethernet driver: MOTO ENET -> ENET
- Reformat boot messages
- Enable redundant environment
- Replace the -O2 optimization flag with -mno-string
2005-03-15 22:56:53 +00:00
wdenk
42d1f0394b * Patches by Xianghua Xiao, 15 Oct 2003:
- Added Motorola CPU 8540/8560 support (cpu/85xx)
  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
  - Added Motorola MPC8560ADS board support (board/mpc8560ads)

* Minor code cleanup
2003-10-15 23:53:47 +00:00