Commit graph

51187 commits

Author SHA1 Message Date
Konstantin Porotchkin
995a9f425d arm64: mvebu: gpio: Add GPIO nodes to A8K family devices
Add GPIO nodes to AP-806 and CP-110-master DTSI files.

Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29 07:38:08 +02:00
Philipp Tomsich
524dd45e0d dtoc: make ScanTree recurse into subnodes
Previously, dtoc could only process the top-level nodes which led to
device nodes in hierarchical trees to be ignored. E.g. the mmc0 node
in the following example would be ignored, as only the soc node was
processed:

  / {
	soc {
		mmc0 {
			/* ... */
		};
	};
  };

This introduces a recursive helper method ScanNode, which is used by
ScanTree to recursively parse the entire tree hierarchy.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-29 07:38:08 +02:00
Jean-Jacques Hiblot
1fb6921e19 drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register
We used to get the address of the optionnal ctrl_mod_mmap register as the
third memory range of the "reg" property. the linux driver moved to use a
syscon instead. In order to keep the DTS as close as possible to that of
linux, we move to using a syscon as well.

If SYSCON is not supported, the driver reverts to the old way of getting
the address from the 3rd memory range

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-03-29 07:38:07 +02:00
Jean-Jacques Hiblot
5c8ef35980 regmap: use fdt address translation
In the DTS, the addresses are defined relative to the parent bus. We need
to translate them to get the address as seen by the CPU core.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-03-29 07:38:07 +02:00
Lokesh Vutla
d666558042 dm: core: Fix Handling of global_data moving in SPL
commit 2f11cd9121 ("dm: core: Handle global_data moving in SPL")
handles relocation of GD in SPL if spl_init() is called before
board_init_r(). So, uclass_root.next need not be initialized always
and accessing uclass_root.next->prev gives an abort. Update the
uclass_root only if it is available.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-03-29 07:38:07 +02:00
Stefan Roese
7a92652346 mmc: xenon_sdhci: Add missing host->max_clk to Xenon SDHCI driver
The Xenon SDHCI driver just missed the integration of this patch:

git ID 6d0e34bf
mmc: sdhci: Distinguish between base clock and maximum peripheral frequency

With this patch applied, the SDHCI subsystem complains now with this warning
while probing:

sdhci_setup_cfg: Hardware doesn't specify base clock frequency

This patch fixes this issue, by providing the missing host->max_clk
variable to the SDHCI subsystem.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Hu Ziji <huziji@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-03-29 07:38:07 +02:00
Xu Ziyuan
6f730459d9 mmc: drop unnecessary send_status request
It's redundant to send cmd13 after cmd9 whose response is not R1b. The
card devices will not be busy w/ cmd9.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-03-29 07:38:07 +02:00
Kevin Liu
5b3e5b5696 mmc: sdhci: only flush cache for data command
No need to flush cache for command without data.

Signed-off-by: Kevin Liu <kevinliu@asrmicro.com>
2017-03-29 07:38:06 +02:00
Felipe Balbi
aff32df522 mmc: tangier: Add Intel Tangier eMMC/SDHCI driver
This patch adds Intel Tangier eMMC/SDHCI driver.

Intel Tangier SoC contains a hybrid of PCI and non-PCI devices. SDHCI
controller is one of the devices which are *not* on a PCI and, hence,
cannot be enumerated by standard PCI means. This driver, allows for
SDHCI controller on Tangier SoC to work in U-Boot.

Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-03-29 07:38:06 +02:00
Felipe Balbi
ac9c4912c0 mmc: pci: Add CONFIG_MMC_PCI
We don't want pci_mmc to compile every time x86 compiles, only when
there's a platform that needs it. For that reason, we're adding a new
CONFIG_MMC_PCI which platforms can choose to enable.

Suggested-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-03-29 07:38:06 +02:00
Bharat Bhushan
78be6222b0 pcie-layerscape: Fixup iommu-map property of pci node
This patch fixup iommu-map property on pci node to have a valid
mapping of requester-id to stream-id. The requester-id to stream-id
mapping is based on PCI-LUT table initialization.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:54:09 -07:00
Bharat Bhushan
47d1736231 pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs
Layerscape Chasis-2 also uses same PCIe controller as Chasis-3
and have similar PCI-Lut.

Signed-off-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:52:41 -07:00
Bharat Bhushan
9f076dbe7e armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1012a
LS1012A is Chassis-2 type SOC and shares same streamid definition.
This patch adds using streamids for ls1012a

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:51:32 -07:00
Bharat Bhushan
b52a05076c armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1046a
LS1046A is Chassis-2 type SOC and shares same streamid definition,
this patch adds using streamids for LS1046A.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:49:51 -07:00
Bharat Bhushan
5344c7b783 arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2
Layerscape Chassis-2 have PCIe device, some platform devices and
DPAA1 devices which will use stream-ids for iommu level isolation
as they are behind SMMU.

This patch defines the stream-ids for Chassis-2 devices. DPAA1 is
reserved for future use.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:47:16 -07:00
Bharat Bhushan
a4954f9467 armv8: fsl-lsch3: Rewrite comment for stream IDs
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared
same stream-id partitioning. This patch rewords the definition to
support all these SOCs.

Also have changes in description about iommu-map property updates
in PCI node.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:44:47 -07:00
Bharat Bhushan
08c5130d28 armv8: fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
The stream ID allocation for Chasis 3.0 devices can be shared among
LS1088, LS2088 and LS2080.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:42:24 -07:00
Hou Zhiqiang
f6bf0a2b14 fsl-layerscape/ls104xardb: enable PPA support for eMMC/SD and NAND boot
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:41:49 -07:00
Hou Zhiqiang
77bbe55d92 armv8: Kconfig: fsl-ppa: support load PPA from eMMC/SD and NAND Flash
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:41:09 -07:00
Hou Zhiqiang
75ce8ee4e4 fsl: PPA: add support PPA image loading from NAND and SD
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:40:09 -07:00
Hou Zhiqiang
203db38a94 mtd: nand: remove nand size print from nand_init function
Add nand_size() function to move the nand size print into initr_nand().
Remove nand size print from nand_init() to allow other function to call
nand_init() without printing nand size.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:39:33 -07:00
Hou Zhiqiang
d72158c045 mtd: nand: add initialization flag
Add initialization flag to avoid initializing NAND Flash multiple
times, otherwise it will calculate a wrong total size.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:38:37 -07:00
Yingxi Yu
132a1468dc armv8/fsl-layerscape: fdt: Skip checking USB clock on LS1012A
USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided
instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup.

Signed-off-by: Yingxi Yu <yingxi.yu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:13:46 -07:00
Wenbin Song
7f33963289 armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on NOR flash
Fix the offsets of MTD partitions on Nor flash on ls1043ardb,
ls1043aqds and ls1046aqds boards. Delete the rcw, uboot env and fman
partitions. Add user partitions for general usage.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:31:10 -07:00
Santan Kumar
54ad7b5ab8 board: freescale: ls2080a/ls2088a: Enable PPA
Enable PPA on LS2080A, LS2088A boards:
-LS2080ARDB, LS2080AQDS
-LS2088ARDB, LS2088AQDS

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:27:58 -07:00
Hou Zhiqiang
0aaa1a90b3 pci: layerscape: Fixup device tree node for ls2088a
LS2088A and its variants have different PCIe node than LS2080A.
The compatible string is updated accordingly.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:22:18 -07:00
Hou Zhiqiang
3d8553f0a3 pci: layerscape: add LS2088A series SoC pcie support
The LS2088A series SoCs has different physical memory map address and
CCSR registers address against LS2080A series SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:21:13 -07:00
yuan linyu
33ed57495a tools: plbimage support generate rcw file
some system will not generate pbl format u-boot, but require rcw.

Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:19:18 -07:00
Ashish kumar
dd48f0bfb5 armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203
This i2c errata only applies to LS2080A and its variants, namely
LS2080A, LS2085A and LS2088A.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:17:07 -07:00
Suresh Gupta
2652a28fee armv8: dts: fsl-ls1012a: Change number of CS in SPI node
LS1012A has only one chip select for QSPI flash.

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:15:58 -07:00
Suresh Gupta
38a5c57ac5 spi: fsl_qspi: Add support for single chip select
SOC’s like LS1012A has only one chip select signal for QSPI flash.
Avoid scanning other flash.

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:10:12 -07:00
Prabhakar Kushwaha
7b45b383fd armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding
SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.

So Avoid RCWSR28 register hard-coding.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:09:22 -07:00
Prabhakar Kushwaha
1b7dba990f arm: fsl-layerscape: Move QSGMII wriop_init to SoC file
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.

So move QSGMII wriop_init_dpmac() to SoC file.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:08:25 -07:00
Priyanka Jain
eea1cb77ce armv8/fsl-layerscape: Update erratum A009635 implementation
Erratum A009635 is valid only for LS2080A SoC and its
personality. Add SoC svr check.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:07:06 -07:00
Hou Zhiqiang
d170aca1a0 pci: layerscape: enable PCIe config ready
In EP mode, to enable accesses from the Root Complex, the
CONFIG_READY bit must be set, otherwise any config attempts
from the Root Complex will be returned with config retry
status (CRS).

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:06:11 -07:00
Udit Agarwal
ac55dadb1c fsl: Secure Boot: Enable IE (Key extention) Feature
For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a verified table of public
keys can be used. The latter feature is called IE Key Extension
Feature.

For Layerscape Chasis 3 based platforms, IE table is validated by
Bootrom and address of this table is written in scratch registers 13
and 14 via PBI commands.

Following are the steps describing usage of this feature:

1) Verify IE Table in ISBC phase using keys stored in fuses.
2) Install IE table. (To be used across verification of multiple
   images stored in a static global structure.)
3) Use keys from IE table, to verify further images.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:03:04 -07:00
Santan Kumar
6d7b9e78f5 armv8: ls2080ardb, ls2080aqds: Add mcmemsize in default env setting
Initialize mcmemsize to 0x40000000

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:01:44 -07:00
Hou Zhiqiang
9e052d9750 fsl-layerscape/ppa: cleanup ppa.h
Moved the ifdef into ppa.h and removed the duplicated macros.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 08:59:47 -07:00
Udit Agarwal
a8c6fd4ec1 armv8: LS2080A: Move sec_init to board_init
Moves sec_init to board_init rather than in misc_init function beacuse
PPA will be initialised in board_init function and for PPA validation
sec_init has to be done prior to PPA init.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 08:58:46 -07:00
Udit Agarwal
350e16cfb4 armv8: lsch3: SECURE_BOOT: Define CONFIG_SYS_LS_PPA_ESBC_ADDR for LS2080A
Add header address for PPA to be validated during ESBC phase for LS2080A
platform based on Layescape Chasis 3.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 08:56:33 -07:00
Lukasz Majewski
e46f8a3309 i2c: Set default I2C bus number
This patch allows using i2c commands (e.g. "i2c probe", "i2c md", etc)
without the need to first select the bus number with e.g. "i2c dev 0".

This is the "i2c" command behavior similar to the one from pre DM, where
by default bus 0 was immediately accessible.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28 06:27:54 +02:00
Lukasz Majewski
b52a3fa08b i2c: ti: Update method to calculate psc, sscl and ssch I2C parameters
This patch updates the way in which psc, sscl and ssch I2C parameters are
calculated to be in sync with v4.9 Linux kernel
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c

The previous method was causing several issues:
- The internal I2C frequency (after prescaler) was far above recommended
one (7 - 12 MHz [*]) - the current approach brings better noise suppression
(as stated in Linux commit: SHA1: 84bf2c868f3ca996e5bb)

- The values calculated (psc, sscl and ssch) were far from optimal, which
caused on the test platform (AM57xx) the I2C0 SCL signal low time (Fast
Mode) of ~1.0us (the standard requires > 1.3 us).

[*] for AM57xx TRM SPRUHZ6G, Table 24,7
"HS I2C Register Values for Maximum I2C Bit Rates in I2C F/S, I2C HS Modes"

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28 06:27:42 +02:00
Lukasz Majewski
e530d2e15b i2c: ti: Update SCLH and SCLL to be in sync with v4.9 Linux kernel
v4.9 Linux release:
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c

recommends to use SCLH=5 and SCLL=7 values.
This patch sets them to default.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28 06:27:33 +02:00
Liam Beguin
0f5b461b9b i2c: lpc32xx: Force consistent bus numbering
Normally, this would probably be done by adding devicetree aliases
to the main dtsi file for the lpc32xx and using bus->req_seq instead.

Since we want to have consistent i2c numbering, we cannot force the
bus->req_seq because. If for instance we have 3 buses numbered
from 0 to 2 with i2c0 enabled, i2c1 disabled and i2c2 enabled;
i2c2 can be selected using 'i2c dev 1' and 'i2c dev 2' commands
because a bus can be probed using req_seq or seq interchangeably.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:27:20 +02:00
Liam Beguin
fb05788013 i2c: lpc32xx: Move definitions to header file
Since the lpc32xx i2c driver does not yet support the devicetree bindings,
this structure is also needed by the board file as the hardware description
is done there.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:27:14 +02:00
Sylvain Lemieux
ddfd082169 i2c: lpc32xx: Remove note for DM conversation
Removed note in the LPC32xx I2C driver for DM conversation.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:27:08 +02:00
Liam Beguin
d61c7adbff i2c: lpc32xx: Add DM for lpc32xx I2C
Adding DM specific wrapper functions and definitions.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:26:39 +02:00
Liam Beguin
eddac8e9fe i2c: lpc32xx: Factor out i2c_adapter parameter
This is part of the prep work for the migration to the driver model.
It will enable the driver to support DM and non-DM configurations
using the same functions.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:26:30 +02:00
Liam Beguin
552531e45d i2c: lpc32xx: Prepare compatibility functions
This is part of the prep work for the migration to the driver model.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:26:16 +02:00
Liam Beguin
03d924ae76 i2c: lpc32xx: Rename probe function
This is part of the prep work for the migration to the driver model.
What used to be the probe function is now called probe_chip.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28 06:26:06 +02:00