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51187 commits

Author SHA1 Message Date
Philipp Tomsich
e92e580350 rockchip: ARM64: puma-rk3399: get DRAM size from DMC init
With the RK3399 DRAM controller (DMC) driver providing all the
infrastructure, retrieve the DRAM size from the DMC init in the
board-specific code (instead of hard-coding) for the RK3399-Q7 (Puma).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
a70feb4620 rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NS
The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS.
To allow us to add a efuse-driver (and more importantly, to allow
probes of such a driver to succeed), we need need to accept requests
for PCLK_EFUSE1024NS and return a non-error result.

As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't
implement any logic to manage this clock gate and simply assume that
the reset-default has not been changed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
a83444ee34 rockchip: add defconfig for firefly-rk3399
The file is from evb-rk3399_defconfig with changes:
- use rk3399-firefly dtb
- re-order by make savedefconfig

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
5540e25aeb dm: sandbox: pwm: add test for pwm_set_invert()
Add test case for new interface set_invert().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix typo in subject and build error in sandbox_pwm_set_invert():
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
1df7ee573e doc: dtbinding: add pwm binding file
This is a copy from kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
874ee59acc rockchip: pwm: implement pwm_set_invert()
Rockchip pwm need to init polarity, implement pwm_set_invert()
to do it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
0b60111aa6 power: regulator: pwm: support pwm polarity setting
The latest kernel PWM drivers enable the polarity settings. When system
run from U-Boot to kerenl, if there are differences in polarity set or
duty cycle, the PMW will re-init:
  close -> set polarity and duty cycle -> enable the PWM.
The power supply controled by pwm regulator may have voltage shaking,
which lead to the system not stable.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
a66726838e rockchip: dts: add rk3399-firefly dts
Firefly-rk3399 is a bord from T-Firefly, you can find detail about
it here:
http://en.t-firefly.com/en/firenow/Firefly_RK3399/

This patch add basic node for the board and make it able to bring
up.

Peripheral/interfaces on board:
- usb hub which connect to ehci controller;
- UART2 debug
- eMMC
- PCIe
- USB 3.0 HOST, type-C port
- sdio, sd-card
- HDMI
- Ethernet
- OPTICAL
- WiFi/BT
- MIPI CSI/DSI
- IR
- EDP/DP

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
dde2223372 rockchip: dts: rk3399: sync with kernel dts
The kernel dts has update a lot since the first time we commit rk3399.dtsi,
sync with kernel for further development.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Simon Glass
439c947f32 dtoc: Handle nodes with phandles that depend on the same
At present dtoc assumes that nodes which are phandles do not themselves
reference other phandle nodes. Unfortunately this is not necessarilly
true. As a result we can currently output C code which does not compile
because a node declaration can be referenced before it is declared.

Adjust the code to explicitly output all phandle nodes needed by node
before the node itself is output.

This fixes building with the latest rk3399-firefly.dts from Linux, which
has reordered the nodes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-05-10 13:37:21 -06:00
Simon Glass
49eec8c7f1 dtoc: Move the output code into its own function
The code to generate the tables is quite long. Move the node-output code
into its own function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
ff71f9ac33 rockchip: mmc: handle deprecation of 'clock-freq-min-max'
The 'clock-freq-min-max' property was deprecated in the upstream
(i.e. Linux) DTS bindings in favor of the 'max-frequency' property.

With the latest RK3399 DTSI does no longer include the deprecated
property and the rockchip_dw_mmc driver requiring it to be present,
the driver doesn't bind to the node in the RK3399 DTSI any longer
(thus breaking access to the SD card on the RK3399-Q7 board).

To fix this, we implement a similar logic as in the Linux driver: if
the deprecated property is present, we issue a warning (if DEBUG is
enabled); if it is missing, we require 'max-frequency' to be set and
use it to create a min/max value-pair.

See b023030f10
for the deprecation/matching change in Linux.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
998c61ae60 rockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTS
The clocking of the designware MMC controller in the upstream
(i.e. Linux) RK3399 has changed/does not match what the current DTS in
U-Boot uses: the first clock entry now is HCLK_SDMMC instead of
SCLK_SDMMC.

With the simple clock driver used for the RK3399, this needs a change
in the selector understood by the various case statements in the driver
to ensure that the driver still loads successfully.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
fa1392a236 rockchip: reserve memory for rk3399 ATF data
There are 3 regions used by rk3399 ATF:
- bl31 code, located at 0x10000;
- cortex-m0 code and data, located at 0xff8c0000;
- bl31 data, located at 0xff8c1000 ~ 0xff8c4000;

SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory
for ATF data, or else there will be memory corrupt after SPL
loads the ATF image.

More detail about cortex-M0 code in ATF:
https://github.com/ARM-software/arm-trusted-firmware/commit/
8382e17c4c6bffd15119dfce1ee4372e3c1a7890

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
602778d3c7 rockchip: pinctrl: rk3399: add gmac io strength support
GMAC controller need to init the tx io driver strength to 13mA,
just like the description in dts pinctrl node, or else the controller
may only work in 100MHz Mode, and fail to work at 1000MHz mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
fd9884e292 rockchip: dts: evb-rk3399: add gmac support
Enable gmac for evb-rk3399.

Change-Id: I85e35667e08e22e38577e63eb0e65731fc9c69b6
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-05-10 13:37:21 -06:00
Kever Yang
76e1693b9b rockchip: rk3399: use actual dram size
Since our sdram driver is ready, we can use the actual size
instead of hard code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Eddie Cai
7474bbe857 rockchip: enable debug uart
enable debug uart for rk3288 and print something to let people know
where we are

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
26b1edf4ce rockchip: dts: evb-rk3399: correct pwm3 polarity
The pwm3 on evb-rk3399 is used for pwm regulator, need to invert
the polarity to make it work correctly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
572045b6e7 rockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma
With the validation done for DDR3-1600 (i.e. 800 MHz bus clock), we
add the timings (rk3399-sdram-ddr3-1600.dtsi) and change rk3399-puma.dts
to use these by default.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop blank line at end of file:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
c5f99c654e rockchip: dts: Clean up graffiti in rk3399-sdram-ddr3-1333.dtsi
The DDR3-1333 timings for the RK3399-Q7 (Puma) has some unintended
left-over comments in them. This change cleans the file up.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
253c60a557 rockchip: mkimage: remove placeholder functions from rkimage
The imagetool framework checks whether function pointer for the verify,
print and extract actions are available and will will handle their
absence appropriately.

This change removes the unnecessary functions and uses the driver
structure to convey available functionality to imagetool.  This is in
fact better than having verify just return 0 (which previously broke
dumpimage, as dumpimage assumed that we had handled the image and did
not continue to probe further).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
24aae93f97 rockchip: mkimage: play nice with dumpimage
Dumpimage (it invoked with "-T rkspi" or "-T rksd") would not work due
to check_params failing. These changes ensure that we can both be called
with an empty imagename.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
a1a2dfb870 rockchip: mkimage: clarify header0 initialisation
This change set adds documentation to the header0 initialisation and
improves readability for the calculations of various offsets/lengths.

As the U-Boot SPL stage doesn't use any payload beyond what is covered
by init_size, we no longer add RK_MAX_BOOT_SIZE to init_boot_size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
c25b8c3af1 rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
ea3729e23b rockchip: mkimage: Update comments for header size
The calculation of the variable header size in rkcommon_vrec_header
had been update twice in the earlier series (introducing boot0-style
images to deal with the alignment of the first instruction in 64bit
binaries). Unfortunately, I didn't update the comment twice (so it
remained out-of-date).

This change brings the comment back in-sync with what the code is
doing.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
366aad4d97 rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images
In (first) breaking and (then) fixing the rkspi tool, I realised that
the calculation of the required padding (for the header-size and the
2K-in-every-4K SPI layout) was not as self-explainatory as it could
have been.  This change rewrites the code (using new, common functions
in rkcommon.c) and adds verbose in-line comments to ensure that we
won't fall into the same pit in the future...

Tested on the RK3399 (with has a boot0-style payload) with SD/MMC and SPI.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
798c93faf3 rockchip: mkimage: rkspi: include the header sector in the SPI size calculation
Our earlier change broke the generation of SPI images, by excluding the
2K used for header0 from the size-calculation.

This commit makes sure that these are included before calculating the
required total size (including the padding from the 2K-from-every-4K
conversion).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
3e75c07ddb rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL
To include the ability to load from an SPI flash in SPL, it's not
sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
is already enabled for SPL via Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Jakob Unterwurzacher
cdeb4d780a rockchip: spi: enable support for the rk_spi driver for the RK3399
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399.  This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.

This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
315e6a38f9 rockchip: pinctrl: rk3399: add support for the SPI5 controller
This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
 * grf_rk3399.h: adds definition for configuring the SPI5 pins
   		 in the GPIO2C group
 * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
   		     PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
		     through SPI5 to the appropriate pin-config
		     function; implements the pin-configuration
		     for PERIPH_ID_SPI5 using the GPIO2C group

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
9fc354e246 rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting
The baudrate in rkspi was calculated by using an integer division
(which implicitly discarded any fractional result), then rounding to
an even number and finally clamping to 0xfffe using a bitwise AND
operator.  This introduced two issues:
1) for very small baudrates (overflowing the 0xfffe range), the
   bitwise-AND generates rather random-looking (wildly varying)
   actual output bitrates
2) for higher baudrates, the calculation tends to 'err towards a
   higher baudrate' with the actual error increasing as the dividers
   become very small. E.g., with a 99MHz input clock, a request
   for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use
   (which amounts to a 23.75% error)... for a 34 MBit request this
   would be an actual outbout of 49.5 Mbit (i.e. a 45% error).

This change rewrites the divider selection (i.e. baudrate calculation)
by making sure that
a) for the normal case: the largest representable baudrate below the
   requested rate will be chosen;
b) for the denormal case (i.e. when the divider can no longer be
   represented), the lowest representable baudrate is chosen.

Even though the denormal case (b) may be of little concern in real
world applications (even with a 198MHz input clock, this will only
happen at below approx. 3kHz/3kBit), our board-verification team kept
complaining.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
bd37671434 rockchip: spi: rk_spi: dynamically select an module input rate
The original clock/bitrate selection code for the rk_spi driver was a
bit limited, as it always selected a 99MHz input clock rate (which
would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL
if a bitrate higher than 48MHz was requested.

To give us better control over the bitrate (i.e. add more operating
points, especially at "higher" bitrate---such as above 9MBit/s), we
try to choose 4x the maximum frequency (clamped to 50MBit) from the
DTS instead of 99MHz... for most use-cases this will yield a frequency
of 198MHz, but is flexible to go beyond this in future configurations.

This also rewrites the check to allow frequencies of up to half the
SPI module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency and does away with the -EINVAL
when trying to select a bitrate (for cases that exceeded the hard
limit) and instead consistently clamps to the lower of the hard limit,
the soft limit for the SPI bus (from the DTS) or the soft limit for
the SPI slave device.

This replaces
  "rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399"
  "rockchip: spi: rk_spi: improve clocking code for the RK3399"
from earlier versions of this series.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
beb90a53f3 rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
which had been mindlessly following the template of the i2c_set_rate
implementation) miscalculates the rate returned due to a off-by-one
error resulting from the following sequence of events:
  1. calculates 'src_div := src_freq / target_freq'
  2. stores 'src_div - 1' into the register (the actual divider applied
     in hardware is biased by adding 1)
  3. returns the result of the DIV_RATE(src_freq, src_div) macro, which
     expects the (decremented) divider from the hardware-register and
     implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')

This can be observed with the SPI driver, which sets a rate of 99MHz
based on the GPLL frequency of 594MHz: the hardware generates a clock
of 99MHz (src_div is 6, the bitfield in the register correctly reads 5),
but reports a frequency of 84MHz (594 / 7) on return.

To fix, we have two options:
 * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't
   make for a particularily nice read
 * we simply call the i2c/spi_get_rate function (introducing additional
   overhead for the additional register-read), which reads the divider
   from the register and then passes it through the DIV_RATE macro

Given that this code is not time-critical, the more readable solution
(i.e. calling the appropriate get_rate function) is implemented in this
change.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
8fa6979beb rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.

Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
eric.gao@rock-chips.com
da10dd1a72 rockchip: video: Makefile: Modify Makefile for rockchip video driver
Modify Makefile for rockchip video driver according to Kconfig, so that
source code will not be compiled if not needed.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
eric.gao@rock-chips.com
b98f0a3d97 rockchip: video: Kconfig: Add Kconfig for rockchip video driver
1. add Kconfig for rockchip video driver, so that video port can be
selected as needed.
2. move VIDEO_ROCKCHIP option to new Kconfig for concision.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop indenting in Kconfig:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
90c9127e47 rockchip: rk3399: correct memory region
RK3399 device memory region is 0xf8000000~0xffffffff.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Xu Ziyuan
85c91cb694 rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Xu Ziyuan
45112271ef rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Xu Ziyuan
7a25a63c13 rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Xu Ziyuan
7f0cfe478b rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Xu Ziyuan
480a9b834c mmc: dw_mmc: rockchip: select proper card clock
As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is
used for communication between host and card devices. The real bus clock
is ciu, so let's rectify it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
68d12600b1 mkimage: rockchip: add support for rk3328
Add support for rk3328 package header in mkimage tool.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
400b4acf1e rockchip: rk3399: use regulators_enable_boot_on() to init regulator
Use regulators_enable_boot_on() instead of init regulators one by one,
the interface can init all the regulators with regulator-boot-on property.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:20 -06:00
Álvaro Fernández Rojas
a41481bfcb mips: bmips: enable bcm6328-power-domain driver for BCM6328 and BCM63268 boards
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
a1b5e5e7c1 mips: bmips: add bcm6328-power-domain driver support for BCM63268
This driver can control up to 32 power domains.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
9a5cb22fda mips: bmips: add bcm6328-power-domain driver support for BCM6328
This driver can control up to 32 power domains.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
7810fb9547 dm: power: domain: add BCM6328 power domain driver
This allows controlling MISC IDDQ register on BCM6328 SoCs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
6327aa4783 mips: bmips: enable bcm6345-reset driver for all BMIPS boards
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00