Commit graph

21857 commits

Author SHA1 Message Date
Jagannadha Sutradharudu Teki
0f6232801c sf: probe: Add support for flag status polling
From Micron, 512MB onwards, flash requires to poll flag status
instead of read status- hence added E_FSR flag on spectific
flash parts.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:45 +05:30
Jagannadha Sutradharudu Teki
f4f51a8ff8 sf: probe: Add support for erase sector selection flag
SECT_4K, SECT_32K and SECT_64K opeartions are performed to
to specific flash by adding a SECT* flag on respective
spi_flash_params.flag param.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:45 +05:30
Jagannadha Sutradharudu Teki
54024c1566 sf: probe: Add support to clear flash BP# bits
Few of the flashes(Atmel, Macronix and SST) require to
clear BP# bits in flash power ups.

So clear these BP# bits at probe time, so-that the flash
is ready for user operations.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:44 +05:30
Jagannadha Sutradharudu Teki
10ca45d005 sf: probe: Add support for SST_WP
Most of the SST flashes needs to write up using SST_WP, AAI
Word Program, so added a flag param on spi_flash_params table.

SST flashes, which supports SST_WP need to use a WP write
sst_write_wp instead of common flash write.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:44 +05:30
Jagannadha Sutradharudu Teki
b7797422e3 sf: probe: Give proper spacing on flash table params
Given proper spacing between flash table params.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:44 +05:30
Jagannadha Sutradharudu Teki
a74db0a4f3 sf: probe: Add support for AT45DB* flash parts
Added AT45DB* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:44 +05:30
Jagannadha Sutradharudu Teki
26dcc5415b sf: probe: Add support for SST25* flash parts
Added SST25* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-10-07 17:55:43 +05:30
Jagannadha Sutradharudu Teki
74bec16eb5 sf: probe: Add support for S25FL* flash parts
Added S25FL* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:43 +05:30
Jagannadha Sutradharudu Teki
80701e54d3 sf: probe: Add support for W25* flash parts
Added W25* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:43 +05:30
Jagannadha Sutradharudu Teki
db7e258412 sf: probe: Add support for MX25L* flash parts
Added MX25L* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:42 +05:30
Jagannadha Sutradharudu Teki
18500e26ce sf: probe: Add support for GD25* flash parts
Added GD25* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:42 +05:30
Jagannadha Sutradharudu Teki
0d7663fe7d sf: probe: Add support for EN25Q* flash parts
Added EN25Q* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:42 +05:30
Jagannadha Sutradharudu Teki
53752c90e0 sf: probe: Add support for M25P* flash parts
Added M25P* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:42 +05:30
Jagannadha Sutradharudu Teki
4d4ec9927f sf: probe: Add new spi_flash_probe support
Added new spi_flash_probe support, currently added N25Q*
flash part attributes support.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:41 +05:30
Jagannadha Sutradharudu Teki
4d5e29a680 sf: Divide spi_flash into multiple parts
Divided the spi_flash framework into mutiple parts for
- spi_flash.c:
        spi flash core file, interaction for spi/qspi driver to
        spi_flash framework.
- spi_flash_ops.c
        spi flash preffered operations, erase,write and read.
- spi_flash_probe.c
        spi flash probing, easy to extend probing functionality.

This change will support to extend the functionality in a
proper manner.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-07 17:55:41 +05:30
Thierry Reding
010c480bbf pci: Properly configure prefetchable memory region
Forcibly set hose->pci_prefetch to NULL to make sure it will be setup.
This will help if for any reason callers didn't make sure themselves to
NULL the field.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-07 08:21:23 -04:00
Andre Przywara
f833e790b4 ARM: virtualization: replace verbose license with SPDX identifier
The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S}
predates the SPDX conversion, so the original elaborate license
statements sneaked in.
Fix this by replacing them with the proper abbreviation.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-07 08:21:13 -04:00
Otavio Salvador
0ff5d14662 doc: Fix a typo in the description in doc/README.JFFS2_NAND
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-10-07 08:21:13 -04:00
Otavio Salvador
ce0f28fa82 include/linux/fb.h: Add a missing include for 'list.h'
The modelist data uses the list definition but the 'list.h' header
were not being included. The build failure is bellow:

,----
| In file included from yyyy.c:16:0:
| .../u-boot/include/linux/fb.h:503:19: error: field 'modelist' has incomplete type
|   struct list_head modelist; /* mode list */
|                    ^
| make[1]: *** [yyyy.o] Error 1
| make[1]: Leaving directory `.../u-boot/board/xxx/yyyy'
| make: *** [board/xxx/yyyy/libyyyy.o] Error 2
`----

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-10-07 08:21:13 -04:00
Otavio Salvador
f501991dca mtd: Fix function description in part_validate comment
The part_validate comment had a wrong description of the actions it
does and referenced to non-existent functions while in fact it calls
'part_validate_eraseblock()'.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-10-07 08:21:13 -04:00
Piotr Wilczek
a6abaadcfa power:pmic: prevent data abort for pmic bat command
This patch prevents data abort when pmic bat command is called
on non-batery pmic device.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Lukasz Majewski <l.majewski@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
2013-10-07 08:21:13 -04:00
Andrew Murray
ddd025bb6e usb: Fix error handling in musb_hcd.c
The wait_until_[rx|tx]ep_ready functions return a u8 to indicate success
containing the value 0, 1 or -1. This patch changes the return type to an
int to accommodate the negative return values.

These functions are used in the file using calls such as if (!wait_until...
Where a -1 is returned it is mishandled and treated as success instead of
a CRC error. This patch addresses this.

Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk>
Acked-by: Marek Vasut <marex@denx.de>
2013-10-07 07:43:46 -04:00
Lars Poeschel
6478cde618 pcm051/igep0033: Supply bd_ram_ofs for cpsw driver
Since 2bf36ac638 the BD ram address is
not hardcoded inside cpsw driver any more. Platforms have to supply
their bd_ram_ofs in the platform data to the driver. This commit does
this for pcm051 and igep0033 boards.

Tested-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
2013-10-07 07:43:46 -04:00
Enric Balletbo i Serra
94b32f60fe ARM: IGEP0033: Update timing to run DDR at 400MHz.
We can run the DDR at 400MHz, so update the timings for that purpose.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
2013-10-07 07:43:46 -04:00
Tom Rini
e3cf969205 am335x_evm: Switch to zImage as default rather than uImage
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-07 07:43:46 -04:00
Tom Rini
f835c77fb7 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-10-04 13:17:48 -04:00
Andre Przywara
e261c83aa0 ARM: VExpress: enable ARMv7 virt support for VExpress A15
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the VExpress specific
manner.
There is no need to provide a custom smp_waitloop() function here.

This also serves as an example for what to do when adding support for
new boards.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:57 +02:00
Andre Przywara
d429688754 ARM: extend non-secure switch to also go into HYP mode
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.

While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).

The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.

In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.

The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:55 +02:00
Andre Przywara
ba6a169811 ARM: add SMP support for non-secure switch
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.

So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.

The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.

The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:51 +02:00
Andre Przywara
bb97545565 ARM: trigger non-secure state switch during bootm execution
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:46 +02:00
Andre Przywara
1ef923851a ARM: add C function to switch to non-secure state
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.

We check the availability of the security extensions first.

Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.

Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
   (GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
   (GICD_IGROUPRn = 0xFFFFFFFF)

The core specific GIC setup is then done in the assembly routine.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:43 +02:00
Andre Przywara
16212b594f ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.

Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
   (GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
   (GICC_PMR = 0xFF)

Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.

The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.

After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.

Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:25 +02:00
Andre Przywara
45b940d6f9 ARM: add secure monitor handler to switch to non-secure state
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:27:11 +02:00
Andre Przywara
d75ba503a9 ARM: prepare armv7.h to be included from assembly source
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 08:25:58 +02:00
Tom Rini
0c5274e6f3 Prepare v2013.04-rc4
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-02 14:42:08 -04:00
Tom Rini
6297872cd5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-10-02 11:45:22 -04:00
Albert ARIBAUD
f04c537629 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-10-02 14:53:27 +02:00
Tom Rini
0ae39166b1 Merge branch 'buildman' of git://git.denx.de/u-boot-x86 2013-10-02 08:26:23 -04:00
Albert ARIBAUD
5c8d5b6fc1 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-10-02 08:10:36 +02:00
Simon Glass
4281ad8e7f buildman: Allow make flags to be specified for each board
There are a few make options such as BUILD_TAG which can be provided when
building U-Boot. Provide a way for buildman to pass these flags to make
also.

The flags should be in a [make-flags] section and arranged by target name
(the 'target' column in boards.cfg. See the README for more details.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-10-01 14:39:14 -06:00
Simon Glass
e19d5781ec buildman: Adjust tests for new boards.cfg format
Commit 27af930e9a changed the boards.cfg format
but missed to change the parsing in buildman. A follow-on commit
03c1bb2425 fixed this but missed fixing the
tests.

This patch updates the tests to fit the new Board constructor.

./tools/buildman/buildman -t
<unittest.result.TestResult run=1 errors=0 failures=0>

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-10-01 14:39:06 -06:00
Julius Werner
5077f96f10 usb: ehci: Fix test mode for connected ports
The EHCI controller has some very specific requirements for the USB 2.0
port test modes, which were not closely followed in the initial test
mode commit. It demands that the host controller is completely shut down
(all ports suspended, Run/Stop bit unset) when activating test mode, and
will not work on an already enumerated port.

This patch fixes that by introducing a new ehci_shutdown() function that
closely follows the procedure listed in EHCI 4.14. Also, when we have
such a function anyway, we might as well also use it in
usb_lowlevel_stop() to make the normal host controller shutdown cleaner.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2013-09-27 16:20:52 +02:00
Eric Nelson
ce7a7f5e6b i.MX6DQ/DLS: Add pad MX6_PAD_GPIO_1__USB_OTG_ID
This patch adds the pad to i.MX6DQ and changes the i.MX6DLS
declaration to match the Linux kernel declaration.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-09-27 13:53:35 +02:00
Pierre Aubert
a0a0dacfe8 mx6: Fix use of improper value in enable_ipu_clock
The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize
the CCGR3 register caused an undefined value for CG0.

Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-09-27 13:53:35 +02:00
Fabio Estevam
a05f4ab6cc mx35pdk: Fix error handling in board_late_init()
If smc911x_initialize() fails we should return the error immediately.

While at it, also check the error from cpu_eth_init().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-09-27 13:53:35 +02:00
Fabio Estevam
17cc2362af mx28evk: Propagate the error if cpu_eth_init() fails
If cpu_eth_init() fails we should return the error immediately.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-09-27 13:53:35 +02:00
Fabio Estevam
2cba60ac84 mx28evk: Propagate the error if cpu_eth_init() fails
If cpu_eth_init() fails we should return the error immediately.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-27 13:53:35 +02:00
York Sun
72048bc3f1 tools/imximage.c: Fix compiling warning
Convert set_hdr_func(struct imx_header *imxhdr) to set_hdr_func(void)
to get rid of the warning

warning: ‘imxhdr’ is used uninitialized in this function

Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-09-27 13:53:35 +02:00
Piotr Wilczek
4d6c96711b samsung: trats2: add support for new board Trats2
This patch add support for a new Samsung board Trats2.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-09-25 10:52:33 +09:00
Piotr Wilczek
ecda331463 samsung:common:i2c: add definions for third soft I2C adapter for Trats2 board
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-09-25 10:52:33 +09:00