Avoid the following build errors after the device tree sync:
drivers/spi/mxs_spi.c: In function ‘mxs_spi_probe’:
drivers/spi/mxs_spi.c:327:25: error: ‘struct dtd_fsl_imx23_spi’ has no
member named ‘spi_max_frequency’
327 | priv->max_freq = dtplat->spi_max_frequency;
| ^~
drivers/spi/mxs_spi.c:328:23: error: ‘struct dtd_fsl_imx23_spi’ has no
member named ‘num_cs’
328 | plat->num_cs = dtplat->num_cs;
| ^~
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.
Signed-off-by: Adam Ford <aford173@gmail.com>
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.
Signed-off-by: Adam Ford <aford173@gmail.com>
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.
Signed-off-by: Adam Ford <aford173@gmail.com>
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.
Signed-off-by: Adam Ford <aford173@gmail.com>
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.
Signed-off-by: Adam Ford <aford173@gmail.com>
Now that a unified imx8mn-u-boot is available, remove duplicated
code for generating flash.bin and other common imx8mn peripherals.
Signed-off-by: Adam Ford <aford173@gmail.com>
Multiple boards create duplicate entries in their respective
-u-boot.dtsi files which all basically do the same thing.
To consolidate these and make it easier to make improvements
going forward, consolidate them all into one place.
This file creates a flash.bin image using binman, and supports
LPDDR4, DDR4 and DDR3. Since individual boards use different
peripherals and different UART ports, those entries were kept
in their respective board files, but the spba1 node was addded
which contains all UART1-3 to help facilitate SPL_DM_SERIAL.
Individual users will still need to include their respective
UART and pinctrl nodes for those UARTS.
This consolidated file also supports generating a flash.bin file
which can boot from flexSPI if CONFIG_FSPI_CONF_HEADER is
enabled.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The GW7904 is based on the i.MX 8M Mini SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- microSD connector with UHS support
- LIS2DE12 3-axis accelerometer
- Gateworks System Controller
- IMX8M FEC
- 2x RS232 off-board connectors
- PMIC
- 10x bi-color LED's
- 1x miniPCIe socket with PCIe and USB2.0
- 802.3at Class 4 PoE
- 10-30VDC input via barrel-jack
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.
i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Plus PCIe
- MIPI CSI
- 2x CAN
- Audio Out
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.
i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
Add support for it.
Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP
devicetree file from linux-next tree.
commit <aec8ad34f7f24> (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit)
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam.
General features:
- NXP i.MX8M Plus
- Up to 4GB LDDR4
- 8 eMMC
- Gigabit Ethernet
- USB 3.0, 2.0 Host/OTG
- PCIe 3.0 interface
- I2S
- LVDS
- rest of i.MX8M Plus features
i.Core MX8M Plus needs to mount on top of Engicam baseboards
for creating complete platform solutions.
Add support for it.
Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam devicetree file from linux-next tree.
commit <eefe06b295087> (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM)
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
In order to test that we properly handle watchdog(s) during the "wait
for the user to interrupt autoboot" phase, we need a watchdog device
to be watching us.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
In order to test that U-Boot actually maintains the watchdog device(s)
during long-running busy-loops, such as those where we wait for the
user to stop autoboot, we need a watchdog device that actually does
something during those loops; we cannot test that behaviour via the DM
test framework.
So introduce a relatively simple watchdog device which is simply based
on calling the host OS' alarm() function; that has the nice property
that a new call to alarm() simply sets a new deadline, and alarm(0)
cancels any existing alarm. These properties are precisely what we
need to implement start/reset/stop. We install our own handler so that
we get a known message printed if and when the watchdog fires, and by
just invoking that handler directly, we get expire_now for free.
The actual calls to the various OS functions (alarm, signal, raise)
need to be done in os.c, and since the driver code cannot get access
to the values of SIGALRM or SIG_DFL (that would require including a
host header, and that's only os.c which can do that), we cannot simply
do trivial wrappers for signal() and raise(), but instead create
specialized functions just for use by this driver.
Apart from enabling this driver for sandbox{,64}_defconfig, also
enable the wdt command which was useful for hand-testing this new
driver (especially with running u-boot under strace).
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
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Merge tag 'u-boot-at91-fixes-2023.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2023.01 cycle:
This small fixes set includes an indentation fix for sam9x60 DT and one
name for one pin for sama7g5.
When the imx8mm.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree. This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot. Fix this by adding the spba node to the spl
device tree to restore normal booting.
Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot
board.
Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
When the imx8mm.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree. This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot. Fix this by adding the spba node to the spl
device tree to restore normal booting.
Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot
board.
Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Add Serial Download Protocol support as it is a useful method to
load flash.bin to RAM and run it via 'uuu'.
With this patch, it is possible to start both U-Boot SPL and U-Boot
proper using the following 'uuu'command:
$ uuu -brun spl flash.bin
Based on a patch from Marek Vasut for the imx8mm-mx8menlo board.
Also, to fit the SPL binary into the internal RAM, select CONFIG_LTO
to reduce its size.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Enable DM USB, DM PHY and USB gadget support in imx8mm-mx8menlo SPL
to let the board continue SDP loading of second stage after the first
stage was loaded by BootROM SDP implementation. It is not possible to
jump back into BootROM v1 and let the BootROM implementation continue
the SDP loading, all this has to be performed by the U-Boot CI HDRC
controller driver and SDP protocol implementation, both of which fit
into the SPL just barely.
With this patch, it is possible to start both U-Boot SPL and U-Boot
using e.g. uuu on this board as follows:
$ uuu -brun spl flash.bin
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The signal name of pin PB2 with function F is FLEXCOM11_IO1
as it is defined in the datasheet.
Fixes: 558378a4cd ("ARM: mach-at91: add support for new SoC sama7g5")
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
The indentation went far on the right due to an extra tab for
each pinctrl sub-nodes.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
- dts update and sync for rk356x, rk3288, rk3399 from Linux;
- Add rk3399 EAIDK-610 board support;
- Update for puma-rk3399 board;
- some fix and typo fix in different drivers;
The first production revision of the MX8M Mini Menlo board implements
a hardware change which swaps console UART and another UART connector.
Implement the swap, which maps the console UART back to the way Verdin
console is mapped.
Signed-off-by: Marek Vasut <marex@denx.de>
The GW7903 revision B adds two additional GPIO's to control the
direction of the 2 isolated digital I/O circuits.
Define them as:
- dig1_ctl
- dig2_ctl
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Update the M2 socket gpio hogs such that they are not active on boot by
flagging them as GPIO_ACTIVE_HIGH so that 'output-high' drives high.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Update the UART config gpio hogs such that it is configured for RS232
by default on boot. Additionally rename them to match the names used
on the reset of the venice boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Enable the I2C bus and set a env variable for the reset GPIO of the touch
controller. This allows us to probe the panel in a script.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This adds support for the Kontron Electronics SoM SL i.MX8MM OSM-S
and the matching baseboard BL i.MX8MM OSM-S.
The SoM hardware complies to the Open Standard Module (OSM) 1.0
specification, size S (https://sget.org/standards/osm).
The existing board configuration for the non-OSM SoM is reused and
allows to detect the SoM variant at runtime.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Improve the naming of the regulators to contain the voltage rail
names from the schematic.
Suggested-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
It turns out that it is not necessary to declare the VSELECT signal as
GPIO and let the PMIC driver set it to a fixed high level. This switches
the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5
accordingly.
Instead we can do it like other boards already do and simply mux the
VSELECT signal of the USDHC interface to the pin. This makes sure that
the correct voltage is selected by setting the PMIC's SD_VSEL input
to high or low accordingly.
Reported-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This adjusts the names of the boards and SoMs to the official naming
used by Kontron marketing. These changes also affect devicetree
names and compatibles. The same changes have been submitted to the
Linux kernel.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The new stable configuration is missing the 100mt setpoint, remove
it before updating the config to make sure the changes are separated
cleanly.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Enable the redundant environment feature to allow falling back in case of
storage corruption. The partition layout for the SPI NOR device is added
to the devicetree.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The display isn't and won't be used in U-Boot. Also the display setup
is not yet supported in mainline Linux, so even for cases where the
U-Boot devicetree is passed to the kernel there is currently no use
for this configuration.
Selecting the proper configuration in the kernel FIT image automatically
depending on the detected hardware can be handled by a script in the
environment.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Beside some rather unexciting sync of the DTs from the kernel tree, and
some Kconfig cleanup, there are some improvements for the ARMv5 Allwinner
family, to support boards with the F1C200s (64MB DRAM) better. We will
get actual board support as soon as the DTs have passed the Linux review
process.
There is also support for the X96 Mate TV Box, featuring the H616 SoC and
a full 4GB of DRAM.
Also we found the secret to enable SPI booting on the H616 (pin PC5 must
be pulled to GND), so the SPI boot support patch is now good to go.
Passed the gitlab CI, plus briefly tested on Pine64-LTS, LicheePi Nano,
X96 Mate and OrangePi Zero.
The IPI scheme in OpenSBI has been updated to support 8-core AE350
platform, the plicsw configuration needs to be modified accordingly.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a
compiled for double-float. To link to it we have to adjust how we build
U-Boot.
As U-Boot actually does not use floating point at all this should not
make a significant difference for the produced binaries.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Some boards with the Allwinner F1C100s family SoCs use UART1 for its
debug UART, so define the pins for the SPL and the pinmux name and mux
value for U-Boot proper.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
So far we stated the lack of a lowlevel() init function for the
Allwinner F1C100s board by defining the respective SKIP_* symbol in the
board's defconfig. However we don't expect any *board* to employ such
low level code, so expect this to be never used for the ARMv5 Allwinner
SoCs.
Select the appropriate symbols in the Kconfig, so that we can remove
them from the defconfig, and avoid putting them in future defconfigs for
other boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Traditionally we assumed that every Allwinner board would come with at
least 256 MB of DRAM, and set our DRAM layout accordingly. This affected
both the default load addresses, but also U-Boot's own address
expectations (like being loaded at 160 MB).
Some SoCs come with co-packaged DRAM, but only provide 32 or 64MB. So
far we special-cased those *chips*, as there was only one chip per DRAM
size. However new chips force us to take a more general approach.
Introduce a Kconfig symbol, which provides the minimum DRAM size of the
board. If nothing else is specified, we use 256 MB, and default to
smaller values for those co-packaged SoCs.
Then select the different DRAM maps according to this new symbol, so
that different SoCs with the same DRAM size can share those definitions.
Inspired by an idea from Icenowy.
This is just refactoring: compiled for all boards before and after this
patch: the binaries were identical.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The enable_caches function in architecture-specific board code is only
necessary for V7A CPUs, code for both V8A and ARM926 have already
declared this function.
Only provide our implementation of enable_caches() for V7A CPUs.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Now that a single binary containing TPL/SPL correctly formatted for SPI
flashes and U-Boot proper, can be generated by binman, let's do it.
Also update the documentation to tell the user to use this newly
generated file instead of manually generating and flashing the binaries.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The offset of the SPL payload on Puma is different than for other
Rockchip devices in that it is stored at offset 256K instead of much
further away in the MMC.
Flashing one binary instead of two at different offsets is much more
user friendly so let's migrate to it by modifying the offset in the Puma
specific Device Tree.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Depending on the toolchain used to compile the SPL for Puma RK3399-Q7
module, the board does not boot because the resulting binary is too big
to fit in SRAM.
Let's add a TPL so that there's no need to fiddle with or hack the
defconfig to have a working bootloader.
This follows what's been done for the majority of other RK3399-based
boards.
See the original commit for the first migrations:
bdc0008011 "rockchip: rk3399: update defconfig for TPL"
Unfortunately, the offset in SPI-NOR for U-Boot proper needs to be
modified, since the move from SPL to TPL+SPL for idbloader.img (and the
"only the first 2KB per 4KB blocks are written" "hack" for rkspi format)
increased the size above 256KB. Let's move it to 512KB to, hopefully, be
safe.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Trying to load U-Boot proper from SPL when SPL was not loaded from
SD-Card is currently not working because the SDMMC pins aren't muxed
correctly. It is assumed the BootROM is doing this for us when booting
from SD-Card hence why it's not needed when booting TPL/SPL from
SD-Card.
The pinctrl properties are removed from the SPL DT property removal list
and the pinctrl configuration nodes made available in the SPL DT, in
addition to the pull-up configurations to allow loading U-Boot proper
from SD-Card as a fallback mechanism for SPI-NOR and eMMC.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
On Haikou devkit, it is possible to disable eMMC and SPI-NOR to force
booting from SD card or USB via rkdeveloptool by toggling a switch. This
switch needs to be overridden in software to be able to access eMMC and
SPI-NOR once the device has booted from SD Card. Puma SoM can override
this pin via gpio3_d5.
Until now, fixed regulator device was abused to model this, but since
there's now support for GPIO hogs, let's use it.
Since we want to be able to boot the SPL from SD Card but give it the
ability to load U-Boot proper from a fallback medium such as eMMC and
SPI-NOR, SPL support for GPIO hogs needs to be enabled too. Support for
other kinds of regulators are not needed anymore, so let's disable them.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Specification
- Rockchip RK3399
- LPDDR3 4GB
- TF sd scard slot
- eMMC
- AP6255 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1 work in otg mode
- 12V DC Power supply
The dts file is sync from linux-next[0].
[0]:https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts
Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
UART0 can obviously also be used for debug uart in U-Boot, so let's add
its support.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The check to perform is on CONFIG_SPL_GPIO and not SPL_GPIO.
Because this was never compiled in, it missed an include of cru.h that
was not detected before. Let's include it too.
Also switch to IS_ENABLED in-code check as it is the preferred
inclusion/exclusion mechanism.
Fixes: 07586ee432 ("rockchip: rk3399: Support common spl_board_init")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The check to perform is on CONFIG_SPL_DM_REGULATOR and not
SPL_DM_REGULATOR. Also switch to in-code check instead of ifdefs.
Fixes: 07586ee432 ("rockchip: rk3399: Support common spl_board_init")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com> # Rock960
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Partial sync of rk3288.dtsi from Linux version 5.18
Changed:
only properties and functions that are not yet included
swap some clocks positions
fix some irq numbers
style and sort nodes
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to better compare the Linux rk3288.dtsi version
with the u-boot version update the cpu and gpu nodes.
Changed:
use operating-points-v2
update thermal for all cpus
add labels to all cpus
change gpu compatible
change gpu interrupt names
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to better compare the Linux rk3288.dtsi version
with the u-boot version move thermal sub nodes to the dtsi
file and remove rk3288-thermal.dtsi
Changed:
replace underscore in nodename
remove comments about sensor and ID
use gpu phandle
add #cooling-cells to gpu node
lower critical temparature
remove linux,hwmon property
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The phycore_rk3288 board has a SPL size problem,
so remove phycore_init() function to stay within the limits.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
These hardware register definitions are common for all K3, remove
duplicate data them by moving them to hardware.h.
While here do some minor whitespace cleanup + grouping.
Signed-off-by: Andrew Davis <afd@ti.com>
This matches how this would be done in Linux and these functions
do the alignment for us which makes the code look cleaner.
Signed-off-by: Andrew Davis <afd@ti.com>
This matches what we did for pre-K3 devices. This allows us to build
boot commands that can check for our device type at runtime.
Signed-off-by: Andrew Davis <afd@ti.com>
Move to latest DDR4 1600MT/s for k3-am64-evm based on EMIF tool
v0.08.40.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Move k3-am64-sk to use 1600MT/s LPDDR4 configuration and update to latest EMIF
tool v0.08.40.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Support VBE OS requests / fixups
Minor error-handling tweaks to bootm command
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Merge tag 'dm-pull-18oct22' of https://source.denx.de/u-boot/custodians/u-boot-dm
Update uclass iterators to work better when devices fail to probe
Support VBE OS requests / fixups
Minor error-handling tweaks to bootm command
The H616 SoC uses the same SPI IP as the H6, also shares the same clocks
and reset bits.
The only real difference is a slight change in the pin assignment: the
H6 uses PC5, the H616 PC4 instead. This makes for a small change in
our spi0_pinmux_setup() routine.
Apart from that, just extend the H6 #ifdef guards to also cover the H616,
using the shared CONFIG_SUN50I_GEN_H6 symbol.
Also use this symbol for the Kconfig dependency.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Ivan Shishkin <s45rus@gmail.com>
Update the devicetree files from the Linux kernel, version v6.0-rc4.
This is covering the 32-bit SoCs, from arch/arm/boot/dts/.
This avoids the not backwards-compatible r_intc binding change, to allow
older kernels to boot, but the other nodes are updated.
Not much change here, the vast majority is actually cosmetic: node names
and using symbolic names for the the RTC clocks.
The R40 boards gain DVFS support.
Some A23/A33 tablet DTs are unified into a single file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Update the devicetree files from the Linux kernel, version v6.0-rc4.
This is covering the 64-bit SoCs, from arch/arm64/boot/dts/allwinner.
This avoids the not backwards-compatible r_intc binding change, to allow
older kernels to boot, but the other nodes are updated.
Not much change here, the vast majority is actually cosmetic: node names
and using symbolic names for the the RTC clocks.
Some A64 boards gain some audio nodes.
The H616 DTs are now switched to the version finally merged into the
kernel, which brings some changes, but none affecting U-Boot.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Fix the compilation issue when CONFIG_DEBUG_UART is activated
drivers/serial/serial_stm32.o: in function `debug_uart_init':
drivers/serial/serial_stm32.c:291: undefined reference to \
`board_debug_uart_init'
The board_debug_uart_init is needed for SPL boot, called in
cpu.c::mach_cpu_init(); it is defined in board/st/stm32mp1/spl.c.
But with the removal #ifdefs patch, the function debug_uart_init() is
always compiled even if not present in the final U-Boot image.
This patch adds a file to provided this function when DEBUG_UART and SPL
are activated.
Fixes: c8b2eef52b ("stm32mp15: tidy up #ifdefs in cpu.c")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The PWR regulators don't need be removed as they are already deactivated.
This patches is a alignment with the accepted patch in Linux device tree
in commit a34b42f8690c ("ARM: dts: stm32: fix pwr regulators references
to use scmi").
Fixes: 69ef98b209 ("ARM: dts: stm32mp15: alignment with v5.19")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Fix the frequencies listed in PLL configuration comments to match
the actual frequencies programmed into hardware. Furthermore, add
a comment which explains how those frequencies are calculated, so
it won't be necessary to look it up all over the datasheet and
make more mistakes in the calculation in the future.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add DT for DHCOR Testbench board, which is a testbench for testing of
DHCOR SoM during manufacturing. This is effectively a trimmed down
version of AV96 board with CSI-2 bridge, HDMI bridge, WiFi, Audio and
LEDs removed and used as GPIOs instead. Furthermore, the PMIC Buck3
is always configured from PMIC NVM to cater for both 1V8 and 3V3 SoM
variant.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
In case the regulator-always-on is present in regulator DT node,
the regulator is always reconfigured to the voltage set in DT on
probe, even if regulator_set_value() has been called before. Drop
the property from AV96 U-Boot DT and enable the regulator manually
in code, as the board already reconfigures the Buck3 regulator in
code per PMIC NVM content instead.
Fixes: 0adf10a87b ("ARM: dts: stm32: Configure Buck3 voltage per PMIC NVM on Avenger96")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
There are a couple users of uclass_next_device return value that get the
first device by other means and use uclass_next_device assuming the
following device in the uclass is related to the first one.
Use uclass_next_device_err because the return value from
uclass_next_device will be removed in a later patch.
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is a number of users that use uclass_first_device to access the
first and (assumed) only device in uclass.
Some check the return value of uclass_first_device and also that a
device was returned which is exactly what uclass_first_device_err does.
Some are not checking that a device was returned and can potentially
crash if no device exists in the uclass. Finally there is one that
returns NULL on error either way.
Convert all of these to use uclass_first_device_err instead, the return
value will be removed from uclass_first_device in a later patch.
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Several parts of the ICID table are only necessary for U-Boot proper.
Disable them in SPL. This saves around 500 bytes.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
FSL_IFC should only be selected when booting from NAND flash (or when
NAND_FSL_IFC is enabled). The existing logic does this correctly when
QSPI is also enabled, but not when just booting from SD.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable
our version when it is enabled.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This enables eDMA snooping on the LS1043A and LS1046A. This will allow
marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent.
Oddly, this bit is only documented for the LS1043A, and is marked as
"reserved" in the LS1046ARM. I have tested this patch on the LS1046A
and found that marking i2c0 as dma-coherent works without issue.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Provide a simple sandbox driver for the thermal uclass.
It simply registers and returns 100 degrees C if requested.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is used as delay for gpmi write strobe.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
- Update RISC-V to use 32bit or 64bit toolchains, depending on if we're
building for 32bit or 64bit CPUs. This requires updating the Docker
container as well to have the 32bit toolchain.
The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:
>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:
arch/riscv/cpu/mtrap.S: Assembler messages:
arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Christian Stewart <christian@paral.in>
Reviewed-by: Rick Chen <rick@andestech.com>
