Most drivers use these access methods but a few do not. Update them.
In some cases the access is not permitted, so mark those with a FIXME tag
for the maintainer to check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.
Signed-off-by: Simon Glass <sjg@chromium.org>
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).
Rename some of the latter variables to end with 'plat' for consistency.
Signed-off-by: Simon Glass <sjg@chromium.org>
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.
Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is not necessary anymore, since device_bind_ofnode() does
the same thing and works with both flattree and livetree.
Rename it to indicate that it is special.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel fixes for 2021.01 cycle
This set includes very important fixes for: MMC booting on several
boards, drive strength on sam9x60ek mmc lines, compile issues for
timer.c old driver, removal of unwanted access to sam9x60 bit for
oscillator bypass mode, and eeproms read on sama5d2_icp.
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
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Merge tag 'u-boot-stm32-20201209' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
Update Patrick and my email address with the one dedicated to
upstream activities.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60
have no support for crystal oscillator bypass. Setting this bit might
affect the device functionality.
Fixes: a64862284f ("clk: at91: sam9x60: add support compatible with CCF")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
This patch fixes this clk issue on I2C on imx8qm
=> i2c bus
Bus 3: i2c@5a830000
=> i2c dev 3
Setting bus to 3
Failed to enable ipg clk
Failure changing bus number (-524)
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
A new compatible string is introduced for V3 CCU, because it has a few
extra features available.
Add the compatible string to the clock driver. As the extra features are
not touched, just share the description struct now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
It's possible to chainload U-Boot proper from the vendor firmware in
rk3399 chromebooks, but the way the vendor firmware sets up clocks is
somehow different than what U-Boot expects. This causes the display to
stay devoid of content even though vidconsole claims to work (with
patches in process of being upstreamed).
This is meant to be a rk3399 version of commit d3cb46aa8c ("rockchip:
Init clocks again when chain-loading") which can detect the discrepancy,
but this patch instead checks whether SPL (and therefore the clock init)
was run via the handoff functionality and runs the init if it was not.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
In order to correctly calculate the designware watchdog
timeouts, the watchdog clock is required. Implement required
clocks to facilitate this.
Signed-off-by: Jack Mitchell <ml@embed.me.uk>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
At present we use a 'node' pointer in the of-platadata phandle_n_arg
structs. This is a pointer to the struct driver_info for a particular
device, and we can use it to obtain the struct udevice pointer itself.
Since we don't know the struct udevice pointer until it is allocated in
memory, we have to fix up the phandle_n_arg.node at runtime. This is
annoying since it requires that SPL's data is writable and adds a small
amount of extra (generated) code in the dm_populate_phandle_data()
function.
Now that we can find a driver_info by its index, it is easier to put the
index in the phandle_n_arg structures.
Update dtoc to do this, add a new device_get_by_driver_info_idx() to look
up a device by drive_info index and update the tests to match.
Signed-off-by: Simon Glass <sjg@chromium.org>
We have a test in dtoc for this feature, but not one in U-Boot itself.
Add a simple test that checks that the information comes through
correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
free() checks if its argument is NULL. No need to check it twice.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
The 12d152620d commit fixed the get_rate helper because the set_parent
one did not re-parent the clock device to the new parent. The 4d139f3838
commit allows you to remove this workaround by calling the
clk_get_parent_rate routine.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.
Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
clk-master can have 5 divisors with a field width of 3 bits
on some products.
Change the mask and number of divisors accordingly.
Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix,
e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Some of these were being
fixed every now and then, see:
commit 71ba2cb0d6 ("board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED")
commit a5ada25e42 ("rockchip: clk: fix wrong CONFIG_IS_ENABLED handling")
commit 5daf6e56d3 ("common: console: Fix duplicated CONFIG in silent env callback")
commit 48bfc31b64 ("MIPS: bootm: Fix broken boot_env_legacy codepath")
Fix all files found by `git grep "CONFIG_IS_ENABLED(CONFIG"` by running
':%s/CONFIG_IS_ENABLED(CONFIG_\(\w+\))/CONFIG_IS_ENABLED(\1)/g' in vim.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Since warm reset may optionally set the CLock Manager to'boot mode',
the clock driver should always force the Agilex's Clock Manager to
'boot mode' before the clock driver start configuring the Clock Manager
in SPL.
In SSBL, clock driver will skip the Clock Manager configuration
if it's already being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.
Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
The cell_count argument is required when cells_name is NULL.
This patch adds this parameter in live tree API
- of_count_phandle_with_args
- ofnode_count_phandle_with_args
- dev_count_phandle_with_args
This parameter solves issue when these API is used to count
the number of element of a cell without cell name. This parameter
allow to force the size cell.
For example:
count = dev_count_phandle_with_args(dev, "array", NULL, 3);
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next
First set of u-boot-atmel features for 2021.01 cycle:
This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.
This change introduces a clock driver for SCMI agent devices. When
SCMI agent and SCMI clock drivers are enabled, SCMI agent binds a
clock device for each SCMI clock protocol devices enabled in the FDT.
SCMI clock driver is embedded upon CONFIG_CLK_SCMI=y. If enabled,
CONFIG_SCMI_AGENT is also enabled.
SCMI Clock protocol is defined in the SCMI specification [1].
Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Another "virtual" clock (in the sense that it isn't configurable). This
could possibly be done as a clock in the device tree, but I think this is a
bit cleaner.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
arm64:
- Support for bigger U-Boot images compiled with PIE
microblaze:
- Extend support for LE/BE systems
zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode
zynqmp-r5:
- Fix MPU mapping and defconfig setting.
xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot
cmd:
- pxe: Add fixing for platforms with manual relocation support
clk:
- fixed_rate: Add DM flag to support early boot on r5
fpga:
- zynqmppl: Use only firmware interface and enable SPL build
serial:
- uartlite: Enable for ARM systems and support endians
mmc:
- zynq: Fix indentation
net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64
kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values
bindings:
- Add binding doc for vsc8531
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Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2021.01
arm64:
- Support for bigger U-Boot images compiled with PIE
microblaze:
- Extend support for LE/BE systems
zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode
zynqmp-r5:
- Fix MPU mapping and defconfig setting.
xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot
cmd:
- pxe: Add fixing for platforms with manual relocation support
clk:
- fixed_rate: Add DM flag to support early boot on r5
fpga:
- zynqmppl: Use only firmware interface and enable SPL build
serial:
- uartlite: Enable for ARM systems and support endians
mmc:
- zynq: Fix indentation
net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64
kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values
bindings:
- Add binding doc for vsc8531
fixed-rate driver is not different from clk_fixed_factor and it is required
very early in boot that's why setup flag for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The most of drivers are using '_' instead of '-' in driver name. That's why
sync up these names to be aligned. It looks quite bad to see both in use.
It is visible via dm tree command.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Add master clock (MCK1..MCK4) support for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Add sckc driver compatible with common clock framework. Driver
implements slow clock support for SAM9X60 compatible IPs (in this
list it is also present SAMA7G5's slow clock IP).
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Move clock code to compat.c to allow switching to CCF
without mixing CCF code with non CCF code. This prepares the
field for next commits.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Add helper for clock drivers. These will be used by following
commits in the process of switching AT91 clock drivers to CCF.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
clk_get_by_indexed_prop() retrieves a clock with dev member being set
with the pointer to the udevice for the clock controller driver. But
in case of CCF each clock driver has set in dev member the reference
to its parent (the root of the clock tree is a fixed clock, every
node in clock tree is a clock registered with clk_register()). In this
case the subsequent operations like dev_get_clk_ptr() on clocks
retrieved by clk_get_by_indexed_prop() will fail. For this, get the
pointer to the proper clock registered (with clk_register()) using
clk_get_by_id() before proceeding.
Fixes: 1d7993d1d0 ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Clock re-parenting is not binding the clock's device to its new
parent device, it only calls the clock's ops->set_parent() API. The
changes in this commit re-parent the clock device to its new parent
so that subsequent operations like clk_get_parent() to point to the
proper parent.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
v2: modify title description aspeed:clock -> clock:aspeed
Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Rename the ast2500-scu.h to aspeed-clock.h.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
- Add CCF clocks definitions for iMX6Q enet (ETH)
- Several fixes for CCF framework - the most notable is the one, which
adds get_rate helper to clk-mux.c
- Improvements for clk command - better visibility and alignment.
After adding custom get_rate helper function it was necessary to include
<dm/uclass.h> to avoid warnings about missing uclass_get_device_by_name.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Series-to: u-boot
The previous version of the get_rate helper does not work if the mux
clock parent is changed after the probe. This error has not been
detected because this condition has not been tested. The error occurs
because the set_parent helper does not change the parent of the clock
device but only the clock selection register. Since changing the parent
of a probed device can be tricky, the new version of the get_rate helper
provides the rate of the selected clock and not that of the parent.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
The tests developed for the mux clock are run on the sandbox. They don't
call the clk_mux_set_parent routine and therefore they do not detect
this error.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
The parent->name variable can be used only in case the
uclass_get_device_by_name routine returns successfully.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
The top-level framework flags are passed as parameter to the common
clock framework (ccf) registration routines without being used.
Checks of the flags setting added by the patch have been added in the
ccf test.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Unlike the other clock types, in the case of the gated clock, a new
driver has been developed which does not use the registering routine
provided by the common clock framework.
The addition of the ecspi0 clock to sandbox therefore allows testing
the ccf gate clock.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
After commit 673f659732 ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF need
to provide PTP clock.
On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux
kernel's CCF.
Code in this change models the simplest case when enet reference clock is
generated from 'osc' clock.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This code has been ported from Linux kernel v5.5.5 (tag) and has been
adjusted to U-Boot's DM.
It adds support for correct recognition of IMX_PLLV3_ENET flag in the
clk-pllv3.c driver.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After commit 673f659732 ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF
need to provide IMX6QDL_CLK_ENET.
This change defines the missing clock in i.MX6Q's CCF.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Do not calculate a unused value of n which is overwritten in both branches
of the subsequent if statement.
Identified by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.
To help this tedious work, this commit converts devfdt_get_addr_ptr()
to dev_read_addr_ptr() by coccinelle. I also removed redundant casts
because dev_read_addr_ptr() returns an opaque pointer.
To generate this commit, I ran the following semantic patch
excluding include/dm/.
<smpl>
@@
type T;
expression dev;
@@
-(T *)devfdt_get_addr_ptr(dev)
+dev_read_addr_ptr(dev)
@@
expression dev;
@@
-devfdt_get_addr_ptr(dev)
+dev_read_addr_ptr(dev)
</smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
According to the description of devfdt_get_addr_ptr, this function should
return NULL on failure, but currently it returns (void *)FDT_ADDR_T_NONE.
Fix this by making devfdt_get_addr_ptr return NULL on failure, as
described in the function comments. Also, update the drivers currently
checking (void *)FDT_ADDR_T_NONE to check for NULL.
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no reason to have firmware specific structure in clock driver.
Move it to generic location and also initialize enum values which is based
on https://lore.kernel.org/linux-arm-kernel/20200318125003.GA2727094@kroah.com/
recommended way to go to make sure that values guaranteed by compiler.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds pciesys support in clock driver for
MediaTek MT7622 SoC.
Signed-off-by: Henry Yen <henry.yen@mediatek.com>
Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
This header file should not be included in other header files. Remove it
and use a forward declaration and un-inlining of dev_get_clk_ptr()
instead.
Fix up the kendryte header files to avoid build errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register read/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
This patch adds a simple clock driver for the Marvell Octeon MIPS SoC
family. Its for IO clock rate passing via DT in some of the Octeon
driver, like I2C. So that we don't need to use the non-mainline API
octeon_get_io_clock().
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.
To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/
The semantic patch that makes this change is as follows:
<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Use the _ptr suffixed variant instead of casting. Also, convert it to
dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE.
One curious part is an error check like follows in
drivers/watchdog/omap_wdt.c:
priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
if (!priv->regs)
return -EINVAL;
devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error.
So, this code does not catch any error in DT parsing.
dev_read_addr_ptr() returns NULL on error, so this error check
will work.
I generated this commit by the following command:
$ find . -name .git -prune -o -name '*.[ch]' -type f -print | \
xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/'
I manually fixed drivers/usb/host/ehci-mx6.c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This sync's the clock tables with the official release from
Linux 5.8-RC2 and update r8a774a1_mstp_table from Ref Manual
v1.00.
Signed-off-by: Adam Ford <aford173@gmail.com>
Add SPI support for the RK3328 clock driver
Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.
To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/
The semantic patch that makes this change is as follows:
<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Use the _ptr suffixed variant instead of casting. Also, convert it to
dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE.
One curious part is an error check like follows in
drivers/watchdog/omap_wdt.c:
priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
if (!priv->regs)
return -EINVAL;
devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error.
So, this code does not catch any error in DT parsing.
dev_read_addr_ptr() returns NULL on error, so this error check
will work.
I generated this commit by the following command:
$ find . -name .git -prune -o -name '*.[ch]' -type f -print | \
xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/'
I manually fixed drivers/usb/host/ehci-mx6.c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We use non-dm code to configure the clk settings in order to simplify
dm clk driver in future, so remove the duplicated code from clk driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
