Commit graph

62 commits

Author SHA1 Message Date
Paul Barker
d933d43686 mmc: renesas-sdhi: Drop <common.h>
In line with changes elsewhere, drop inclusion of the common header.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-11-02 11:30:18 +01:00
Paul Barker
fa8422df94 mmc: renesas-sdhi: Fix error handling in rzg2l_sdhi_setup
We should ensure that reset_free() is called in the error path.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Fixes: 93c811b733 ("mmc: renesas-sdhi: Initialize module on RZ/G2L")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-27 11:21:28 +02:00
Paul Barker
93c811b733 mmc: renesas-sdhi: Initialize module on RZ/G2L
On the Renesas RZ/G2L SoC family, we must ensure that the required clock
signals are enabled and the reset signal is de-asserted before we try to
communicate with the SDHI module.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-17 03:27:42 +02:00
Paul Barker
e84dddf10a mmc: renesas-sdhi: Refactor probe function
Move the assignment of priv->quirks earlier in the function. This allows
us to drop the quirks local variable and makes it easier to maintain
clean error handling when we add RZ/G2L support in the next patch.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-17 03:27:42 +02:00
Hai Pham
99ab3d8dc4 mmc: renesas-sdhi: Send stop when MMC tuning command fails
When tuning command (CMD21) fails with command error, call
mmc_send_stop_transmission() to send stop command (CMD12).

Reviewed-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Add dev_dbg() message in case tuning abort fails
        Move tuning opcode check from mmc_abort_tuning()]
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-18 09:17:23 +09:00
Hai Pham
632a7b1186 mmc: renesas-sdhi: Add R-Car Gen4 support
Support R-Car Gen4 family. The default quirk is similar to previous
generation.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use RCAR_64 Kconfig
2023-04-07 17:13:28 +02:00
Marek Vasut
f20a61af42 mmc: renesas-sdhi: Add proper probe error fail path
In case one of the calls in probe fail, trigger a fail path and
undo all the steps done in probe until the point of failure.
The current implementation failed to stop controller clock and
free claimed clock, so fix that. Furthermore, print return code
in error prints for easier debugging.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10 17:45:47 +01:00
Marek Vasut
6ddffa89cb mmc: renesas-sdhi: Always configure default SDnH clock rate to 800 MHz
The prior stage bootloader might have left the SDnCKCR register in completely
arbitrary state before passing control to U-Boot, which includes the register
being populated with incorrect values. Currently the SDHI driver will attempt
to use clock framework to configure SDn clock, which may fail in case SDnCKCR
contains invalid values for the SDnH clock, because the clock framework would
not be able to determine SDnH clock rate and would get -EINVAL instead, which
in turn would not allow the clock framework to determine the correct SDn clock
divider ratio.

This failure occurs specifically in case SDnCKCR reads back 0x209 .

Correct the problem by first setting default SDnH clock rate to 800 MHz, thus
assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn
clock rate to default 200 MHz.

Note that the SDHI driver may reconfigure SDnH clock later based on IOS
settings obtained from the attached card, the 800 MHz set up here is only
the default value.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-10 17:45:47 +01:00
Hai Pham
4dbbc3f373 clk: renesas: Switch to new SD clock handling
The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a separate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.

Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk:
renesas: rcar-gen3: Switch to new SD clock handling") and commit
e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
       - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
       - Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and
         rate = 200000000, the divider would be 0 and table lookup
	 would fail.
       - Turn rcar_clk_get_table_val into signed integer, so it can
         return 0 as a valid value and negative values as errors.
       - Make the code operate on correct clock and add comment
         which explains the reasoning behind it.
       - Rebase on changes to
         clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
2023-02-02 01:49:20 +01:00
Hai Pham
3c78ce8680 mmc: renesas-sdhi: Flag non-standard SDnH handling for V3M
V3M handles SDnH differently than other Gen3 SoCs, so let's add a
separate entry for that. This will allow better SDnH handling in the
future.

Based on Linux commit 627151b4966f ("mmc: renesas_sdhi: Flag
non-standard SDnH handling for V3M") by Wolfram Sang

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
89f9e729be mmc: renesas-sdhi: Drop R-Car H3 ES3.0 HS400 calibration table
It is unnecessary, so clean it up.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message, mention ES3.0
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
d919bb9830 mmc: renesas-sdhi: Add R8A77961 M3-W+ support
Support R8A77961 M3-W+ SoC.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
1cdabcc6a4 mmc: renesas-sdhi: Adjust HS400 calibration offsets for M3-W r1.3
Still uses 0x3 for now, adjust the offset value to TMPPORT3 accordingly

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
af95db514d mmc: renesas-sdhi: Adjust HS400 calibration tables
Adjust HS400 calibration tables based on Linux settings

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
6d7d4c4821 mmc: renesas-sdhi: Filter out HS400 on M3-W r1.2, V3M, V3H r1.x, D3
Further filter out HS400 support on certain SoCs.

Since M3-W r1.2 does not support HS400, drop the calibration table and
rename the one for M3-W r1.3 to r8a7796_rev13_calib_table

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
01cbce80c1 mmc: renesas-sdhi: R-Car M3 r1.3 also uses 4 tuning taps
Early ES revisions of M3-W SoCs requires 4-tap HS400. Reflect the status
from datasheet.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Simon Glass
401d1c4f5d common: Drop asm/global_data.h from common header
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-02 15:33:42 -05:00
Marek Vasut
8a73bef338 mmc: tmio: sdhi: Configure internal DMA bus width
The R-Car3 SDHI should set these two bits in DMA_MODE register according
to the specification, to indicate 64bit bus width. No other bus width
options are permitted and the default value is 0, which is incorrect.
Set the bits accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-01-31 14:08:45 +01:00
Simon Glass
c69cda25c9 dm: treewide: Rename dev_get_platdata() to dev_get_plat()
Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
caa4daa2ae dm: treewide: Rename 'platdata' variables to just 'plat'
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:08 -07:00
Simon Glass
41575d8e4c dm: treewide: Rename auto_alloc_size members to be shorter
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 08:00:25 -07:00
Adam Ford
4ce9566e43 mmc: renesas-sdhi: Enable support for R8A774A1
The r8a774a1 is compatible with the generic rcar-gen3-sdhi controller.
This patch adds the compatibilty flag, to support the SDHI controller.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25 11:16:40 +02:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Marek Vasut
4a66d4ee33 mmc: tmio: sdhi: Implement get_b_max function
Implement get_b_max() for the Renesas R-Car SDHI controller driver, limit
the b_max per hardware capabilities such that select Gen2 controllers have
16bit block transfer limit, the rest has 32bit block transfer limit and on
Gen3, the block transfer limit on addresses above the 32bit boundary is set
to 1/4 of the malloc area.

Originally, on Gen3, the block transfers above the 32bit area were limited
to PIO only, which resulted in (R8A7795 Salvator-X , HS200 eMMC):
  => time mmc read 0x0000000700000000 0 0x10000
  time: 0.151 seconds
  => time mmc read 0x0000000700000000 0 0x100000
  time: 11.090 seconds
with bounce buffer in place and b_max adjustment in place:
  => time mmc read 0x0000000700000000 0 0x10000
  time: 0.156 seconds
  => time mmc read 0x0000000700000000 0 0x100000
  time: 2.349 seconds

Note that the bounce buffer does mallocate and free the bounce buffer
for every transfer. Experiment which removes this results in further
increase of read speed, from 2.349s to 2.156s per 512 MiB of data,
which is not such a significant improvement anymore. It might however
be interesting to have bounce buffer directly in the MMC core or even
block core.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2020-04-22 20:41:56 +08:00
Marek Vasut
d2661d8e9f mmc: tmio: sdhi: Use bounce buffer to avoid DMA limitations
The R-Car SDHI DMA controller has various restrictions. To work around
those restrictions without falling back to PIO, implement bounce buffer
with custom alignment check function which tests for those limitations.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2020-04-22 20:41:56 +08:00
Simon Glass
336d4615f8 dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Marek Vasut
56b0bb96be mmc: tmio: sdhi: Add calibration tables
Instead of using single fixed value for the calibration offset,
add tables which dynamically adjust this per calibration code
from the SCC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
1bdcb83d29 mmc: tmio: sdhi: Skip bad taps
Some of the tuning taps produce suboptimal results. Add code
which skips those "bad" taps.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
6900066cf6 mmc: tmio: sdhi: Add SCC error checking
Check SCC for errors after check command if applicable and
optionally adjust the bus skew settings accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
8f39b03022 mmc: tmio: sdhi: Disable auto-retuning in HS400
Disable the auto-retuning in HS400 mode in favor of manual calibration.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
e5d3f3d9e5 mmc: tmio: sdhi: Adjust HS400 calibration offsets
Adjust the TMPPORT3 offsets according to the latest information
from the chip vendor.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
dc419fc6e1 mmc: tmio: sdhi: Adjust DT2FF settings for HS400 mode
Adjust the DT2FF offsets in HS400 according to latest information
from the chip vendor.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
810998871a mmc: tmio: sdhi: Use 4 tuning taps on M3W up to ES1.2
The M3W up to ES1.2 uses 4 tuning taps for HS400, make it so.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
37c3990664 mmc: tmio: sdhi: Track SMPCMP valu in private data
Retain the SMPCMP value from last calibration in private data.
This will be later used for skipping bad taps.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
0196a58a79 mmc: tmio: sdhi: Track current tap number in private data
Retain the tap number from last calibration in private data. This
will be later used for SCC error checking after each command.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Sam Protsenko
6cf8a903c5 mmc: Rename timeout parameters for clarification
It's quite hard to figure out time units for various function that have
timeout parameters. This leads to possible errors when one forgets to
convert ms to us, for example. Let's rename those parameters
correspondingly to 'timeout_us' and 'timeout_ms' to prevent such issues
further.

While at it, add time units info as comments to struct mmc fields.

This commit doesn't change the behavior, only renames parameters names.
Buildman should report no changes at all.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
2019-09-05 15:27:31 +08:00
Marek Vasut
b5900a58ca mmc: tmio: sdhi: HS400 manual adjustment
Since Gen3 SDHI has an internal DS signal AC-spec violation in HS400 mode,
CRC-error may occur in read command in HS400 mode. This phoenomenon occurs
at low/high temperature.

To fix this, after completion of HS400 tuning, enable manual calibration.
However, Gen3 M3 Ver.1.2 or earlier and H3 1.x does not support HS400.
These SoC forcibly use HS200 mode by SoC attribute.

The DT adjustment of the tuning parameters is not supported until the
DT property names become clear.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Adapted from a patch by Takeshi Saito <takeshi.saito.xv@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Peng Fan <peng.fan@nxp.com>
2019-05-21 22:15:32 +02:00
Marek Vasut
1bac2b6b41 mmc: tmio: sdhi: Minor macro cleanup
Clean up the whitespaces in macros, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Peng Fan <peng.fan@nxp.com>
2019-05-21 22:15:32 +02:00
Marek Vasut
ba41c45ec3 mmc: renesas: Unconditionally set DTCNTL TAPNUM to 8
According to latest specification rev.0026 and after confirmation with
HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on
H3 ES2.0 SoC. Make it so.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-25 16:07:41 +01:00
Marek Vasut
261445dfaf mmc: tmio: sdhi: Configure DT2FF register for HS400 mode
The DT2FF register must be configured differently for HS400 mode
and for HS200/SDR104 mode. Configure the DT2FF register according
to the recommended datasheet settings for each mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-16 18:12:17 +01:00
Marek Vasut
992bcf4f27 mmc: tmio: Make DMA transfer end bit configurable
Different versions of the SDHI core use either bit 17 or bit 20 for the
DTRAEND indication, which can differ even between SoC revisions. Make
the DTRAEND bit position part of the driver private data, so that the
probe function can set this accordingly. Set this to 20 on Socionext
SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-09 11:08:40 +01:00
Marek Vasut
50aa1d99ed mmc: tmio: sdhi: Add HS400 support
Add support for the HS400 mode to SDHI driver. This uses the up-tune
mechanism from already supported HS200 tuning.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-03 12:51:17 +01:00
Marek Vasut
95ead3d98d mmc: tmio: sdhi: Move tap_pos to private data
Move the tap_pos variable, which is the HS200/HS400/SDR104 calibration
offset, into private data, so it can be passed around. This is done in
preparation for the HS400 mode, which needs to adjust this value.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-03 12:51:17 +01:00
Marek Vasut
d34bd2deda mmc: tmio: sdhi: Filter out HS400 on certain SoCs
Filter out HS400 support on SoCs where HS400 is not supported yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-03 12:51:17 +01:00
Marek Vasut
8ec6a04b6b mmc: tmio: Switch to clock framework
Switch the driver to using clk_get_rate()/clk_set_rate() instead of
caching the mclk frequency in it's private data. This is required on
the SDHI variant of the controller, where the upstream mclk need to
be adjusted when using UHS modes.

Platforms which do not support clock framework or do not support it
in eg. SPL default to 100 MHz clock.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
---
V2: - Fix build on certain platforms using SPL without clock framework
V3: - Turn clk_get_rate into a callback and fill it as needed on both
      renesas and socionext platforms
2018-12-03 12:51:16 +01:00
Marek Vasut
a376dde1de mmc: tmio: sdhi: Merge DTCNTL access into single register write
It is perfectly fine to write th DTCNTL TAP count and enable the
SCC sampling clock operation in the same write.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:07:04 +01:00
Marek Vasut
2fc10754d1 mmc: tmio: sdhi: Implement waiting for DAT0 line state
When the bus switches to 1.8V mode of operation, it is necessary to
verify that the card correctly initiated and completed the voltage
switch. This is done by reading out the state of DATA0 line.

This patch implement support for reading out the state of the DATA0
line, so the MMC core code can correctly switch to 1.8V mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:04:45 +01:00
Marek Vasut
dc1488f1d2 mmc: tmio: sdhi: Clear HS400 settings when resetting SCC
Make sure to clear HS400 configuration when resetting the SCC block.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:04:45 +01:00