cm-t54 Eth MAC address is stored in onboard EEPROM.
Add EEPROM support and setup stored Eth MAC address.
If EEPROM does not contain a valid MAC, then generate it from the
processor ID code (reference code is taken from OMAP5 uEvm board file).
Modify Device Tree blob MAC address field with retrieved data.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
As revision code 1 is for silicon revision 2.0, it is easily confused with
silicon revision 1.0.
Device type report also reworked in same style.
Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
Last section of DMM is used for trapping tiler unmapped sections.
Corresponding trap_size should be deducted from total SDRAM size
only if trap section is overlapping with available SDRAM
based on DMM sections. Fixing the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Roger Meier <r.meier@siemens.com>
Tested-by: Samuel Egli <samuel.egli@siemens.com>
This adds the Gumstix DuoVero machine [1]. This is a OMAP4430-based
computer-on-module (COM aka SOM) that can be mounted on various
expansion boards with different peripherals.
[1] https://store.gumstix.com/index.php/category/43/
Signed-off-by: Ash Charles <ash@gumstix.com>
[trini: Rename gpmc_enable_gpmc_cs_config to gpmc_enable_gpmc_net_config]
Signed-off-by: Tom Rini <trini@ti.com>
The omap_hw_init_context function (and assorted helpers) is the same for
all OMAP-derived parts as when CHSETTINGS are used, that's the same and
our DDR base is also always the same. In order to make this common we
simply need to update the names of the define for DDR address space
which is also common.
Cc: Sricharan R. <r.sricharan@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA72 has 1GB connected to EMIF1 only. Updating the details.
And also enable WA for BUG0039 only if corresponding EMIF is present.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>
TPS65917 is used in DRA722 evm. Update the address offsets accordingly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Tom Rini <trini@ti.com>
GPMC controller on TI's OMAP SoC is general purpose controller to interface
with different types of external devices like;
- parallel NOR flash
- parallel NAND flash
- OneNand flash
- SDR RAM
- Ethernet Devices like LAN9220
Though GPMC configurations may be different for each platform depending on
clock-frequency and external device interfacing with controller. But
initialization sequence remains common across all platfoms.
Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c
files into single omap-common/mem-common.c
However, actual platforms specific register config values are still sourced
from corresponding platform specific headers like;
AM33xx: arch/arm/include/asm/arch-am33xx/mem.h
OMAP3: arch/arm/include/asm/arch-omap3/mem.h
OMAP4: arch/arm/include/asm/arch-omap4/mem.h
OMAP4: arch/arm/include/asm/arch-omap5/mem.h
Also, CONFIG_xx passed by board-profile decide config for which set of macros
need to be used for initialization
CONFIG_NAND: initialize GPMC for NAND device
CONFIG_NOR: initialize GPMC for NOR device
CONFIG_ONENAND: initialize GPMC for ONENAND device
Signed-off-by: Pekon Gupta <pekon@ti.com>
[trini: define GPMC_SIZE_256M for omap3]
Signed-off-by: Tom Rini <trini@ti.com>
This patch moves platform specific information for GPMC and ELM controller
into separate header files, so that any derivative devices do not mess other
header files.
Platform specific information added into arch-xx/../hardware.h
- CPU related platform specific details like base-address of GPMC and ELM
Platform specific information added into arch-xx/../mem.h
- Generic configs for GPMC and ELM initialization.
- Hardware parameters or constrains specific to GPMC and ELM IP like;
number of max number of chip-selects available
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch moves platform specific information for GPMC and ELM controller
into separate header files, so that any derivative devices do not mess other
header files.
Platform specific information added into arch-xx/../hardware.h
- CPU related platform specific details like base-address of GPMC and ELM
Platform specific information added into arch-xx/../mem.h
- Generic configs for GPMC and ELM initialization.
- Hardware parameters or constrains specific to GPMC and ELM IP like;
number of max number of chip-selects available
Signed-off-by: Pekon Gupta <pekon@ti.com>
Clean-up the board configuration file for the Gumstix Overo board by
including common omap3 definitions from ti_omap3_common.h as suggested
here [1].
[1] http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/185960
Signed-off-by: Ash Charles <ashcharles@gmail.com>
Conflicts:
include/configs/omap3_overo.h
Update the board configuration for Gumstix Overo. In particular,
add support for zImage and DTB files on boot.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
Add EEPROM ID switches for Alto35, Arbor43C, Stagecoach, Thumbo, and
Turtlecore Gumstix Overo expansion boards.
Signed-off-by: Ash Charles <ash@gumstix.com>
Gumstix Overo COMs with board revision 0x4 use a different Wifi and
Bluetooth module: Wi2Wi's W2CBW0015. No other code changes are required
in u-boot---just handling of this particular board revision.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
Patch f33b9bd3
[arm: omap3: Enable clocks for peripherals only if they are used]
breaks SPL booting on Overo. Since some gpio inputs are
read to detect the board revision. But with this patch above, the
clocks to the GPIO subsystems are not enabled per default any more.
The GPIO banks need to be configured specifically now.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
The linux kernel is at nand0,3 using the current layout, but is best
accessed through the partition label "linux". Since CONFIG_CMD_MTDPARTS is
defined the CONFIG_JFFS2 settings are unreferenced; use "setenv partition
rootfs" to set the default mtd partition for jffs2.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Tested-by: Ash Charles <ash@gumstix.com>
Linux kernel at version 3.5 is about 3.5 MiB; test kernels for 3.10 exceed 4
MiB. Prepare for future upgrades by increasing the NAND partition now.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Tested-by: Ash Charles <ash@gumstix.com>
The NAND linux partition format default was changed from jffs2 to ubi in
254973e6df but the corresponding commands were
not enabled.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Tested-by: Ash Charles <ash@gumstix.com>
Adapted from d70f5480 described below.
commit d70f54808d
Author: Javier Martinez Canillas <javier@dowhile0.org>
Date: Mon Jan 7 03:51:20 2013 +0000
omap4: allow the use of a plain text env file instead boot scripts
For production systems it is better to use script images since
they are protected by checksums and carry valuable information like
name and timestamp. Also, you can't validate the content passed to
env import.
But for development, it is easier to use the env import command and
plain text files instead of script-images.
Since both OMAP4 supported boards (Panda and TI SDP4430) are used
primarily for development, this patch allows U-Boot to load env var
from a text file in case that an boot.scr script-image is not present.
The variable uenvcmd (if existent) will be executed (using run) after
uEnv.txt was loaded. If uenvcmd doesn't exist the default boot sequence
will be started.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Tested-by: Ash Charles <ash@gumstix.com>
Conflicts:
boards.cfg
Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
Apply command "tools/reformat.py -i -d '-' -s 8 <boards.cfg
>boards0.cfg && mv boards0.cfg boards.cfg" in preparation of
pull request from ARM to main tree.
The new 768KB u-boot image size requires changes for
SRIO/PCIE boot. These addresses need to be updated to
appropriate locations.
The updated addresses are used to configure the SRIO/PCIE
inbound windows for the boot, and they must be aligned
with the window size based on the SRIO/PCIE modules requirement.
So for the 768KB u-boot image, the inbound window cannot be set
with 0xfff40000 base address and 0xc0000 size, it should be
extended to 1MB size and the base address can be aligned with
the size.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
AFAICT, c=ffe does nothing and was a typo from the original commit
d17123696c "powerpc/p4080: Add support
for the P4080DS board" and just kept on getting duplicated
in subsequently added board config files.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Edward Swarthout <ed.swarthout@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.
For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.
This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
In case of secure boot from NAND, CSPR and FTIM settings are
same as non-secure NAND boot. CSPR0 is configured as NAND and
CSPR1 is configured as NOR.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
P1020 SoC which has two USB controllers, but only first one is used
on this platform.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T4160RDB shares the same platform as T4240RDB. T4160 is
a low power version of T4240, with the eight e6500 cores,
two DDR3 controllers, and same peripheral bus interfaces.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T104xrdb has several sleep management signals that are used for deep
sleep. They are enabled by OS to enter deep sleep and should be
disabled by u-boot when cores wake up.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
According to AN3638, CRC of NXID v1 is at the end of the
256-byte I2C memory. The wrong CRC32 offset prevents Uboot
from reading system information from EEPROM. No NXID v0 is
being used on Freescale boards.
Signed-off-by: Ebony Zhu <b45385@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds support for VSC8664 PHY module which can
be found on Freescale's T4240RDB boards.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
There is an unfortunate bug in the signoff suppression logic. The first
pass is performed with 'git log', and all signoffs are added to the
supression set, such that the second time (when processing the real
patches) we always suppress the signoffs.
Correct this by only suppressing signoffs in the second pass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Michal Simek <monstr@monstr.eu>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
Because sandbox is not a real hardware, setting vendor=sandbox is
almost meaningless.
This commit sets sandbox's vendor field to '-'.
It is a good thing that it decreases one level directory hierarchy.
The files board/sandbox/sandbox/* have been moved to board/sandbox/*.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This reverts commit 258060905e.
Conflicts:
boards.cfg
Wrong patch 25806090 was applied by accident. Revert it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Exception handling is basically identical for all ARM targets.
Factorize it out of the various start.S files and into a
single vectors.S file, and adjust linker scripts accordingly.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
