As sama5 board has 32k sram size, so the at91bootstrap and spl for sama5
boards is bigger than 16k (0x4000). That will overlap the U-Boot
environment. So I move environment to 0x6000. And reduce its size as
well.
Following shows the size of the spl binaries (v2015.04 vs v2015.07):
% ls v2015.04/*spi*spl.bin -l | awk '{print $5,$(NF)}'
15540 v2015.04/at91sam9n12ek_spiflash_defconfig_u-boot-spl.bin
15704 v2015.04/at91sam9x5ek_spiflash_defconfig_u-boot-spl.bin
16064 v2015.04/sama5d3xek_spiflash_defconfig_u-boot-spl.bin
16304 v2015.04/sama5d4ek_spiflash_defconfig_u-boot-spl.bin
16304 v2015.04/sama5d4_xplained_spiflash_defconfig_u-boot-spl.bin
% ls v2015.07/*spi*spl.bin -l | awk '{print $5,$(NF)}'
16136 v2015.07/at91sam9n12ek_spiflash_defconfig_u-boot-spl.bin
16300 v2015.07/at91sam9x5ek_spiflash_defconfig_u-boot-spl.bin
16664 v2015.07/sama5d3xek_spiflash_defconfig_u-boot-spl.bin
16904 v2015.07/sama5d4ek_spiflash_defconfig_u-boot-spl.bin
16904 v2015.07/sama5d4_xplained_spiflash_defconfig_u-boot-spl.bin
The gcc version is: gcc 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1)
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Bo Shen <voice.shen@gmail.com>
Add 32bpp framebuffer support for the Atmel HLCDC driver. This is
needed for output bpp higher than 16bpp.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Global variables are bad. Get rid of this particular one, so we can
correctly instantiate multiple atmel mci interfaces, without having
them interfere with one another.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Instead of passing just the register area as a private data, introduce
a proper struct atmel_mci_priv structure instead. This will become useful
in the subsequent patch, where we eliminate the global variable from this
driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fix free()]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
After silencing the prints which were generated when reconfiguring the
clock of the SD/MMC bus, surprisingly, the driver stopped working such
that every attempt to use the SD/MMC bus caused the CPU to get totally
stuck hard. It turns out that the prints generated a short delay, which
was necessary for the CPU to reconfigure the clock without getting stuck.
Thus, this patch adds a short delay after the clock configuration instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
This driver generates clearly debugging prints when changing clock
speed, so silence those. Furthermore, the driver generates further
prints in case a command fails to complete. The later case woud be
useful, but for eMMC, command 8 can fail and it's not an error but
a part of the specification. Thus, make this debug() as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
crt0.S do both memset the bss section and call board_init_r for us, so
remove them from board_init_f().
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
As more features are added for SD boot on LS1021A QDS board,
the size of U-Boot is larger. CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS
needs to be adjusted to a suitable value.
Starting address of the malloc pool used in SPL needs to be
adjusted too, or it will occupy the address u-boot loads.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
I2C1 can work on ls102xa rev2.0 SD boot, so add
ID EEPROM for SD boot.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
It will take more than 1s when wake up from deep sleep. Most of the
time is spent on outputing information. This patch reduced the deep
sleep latency by:
1. avoid outputing system informaton
2. remove flush cache after DDR restore
3. skip reloading second stage uboot binary when SD boot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The ITS bit was being read incorrectly beacause of operator
precedence. The same ahs been corrected.
Signed-off-by: Lawish Deshmukh <lawish.deshmukh@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
SR_IE(Self-refresh interrupt enable) is needed for
Hardware Based Self-Refresh. Make it configurable and let
board code handle the rest.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Reviewed-by: York Sun <yorksun@freescale.com>
eth_get_dev() can return NULL which means device_probe() fails for
that ethernet device. Add return value check in various places or
U-Boot will crash due to NULL pointer access.
With this commit, 'dm_test_eth_act' test case passes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
U-Boot crashes when doing a 'ping' with the following test scenario:
- All ethernet devices are not probed
- "ethaddr" for all ethernet devices are not set
- "ethact" is set to a valid ethernet device name
Add a new test case 'dm_test_eth_act' to hit such scenario.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
platdata->enetaddr was assigned to a value in dev_probe() last time.
If we don't clear it, for dev_probe() at the second time, dm eth
will end up treating it as a MAC address from ROM no matter where it
came from originally (maybe env, ROM, or even random). Fix this by
clearing platdata->enetaddr when removing an Ethernet device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
dev->uclass->uc_drv->per_device_auto_alloc_size is to be freed in
device_free(), so is dev->seq. Remove these unnecessary codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In pch_gbe_probe(), some additional resources are allocated
(eg: mdio, phy). We should free these in the driver remove phase.
Add pch_gbe_remove() to clean it up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In designware_eth_probe(), some additional resources are allocated
(eg: mdio, phy). We should free these in the driver remove phase.
Add designware_eth_remove() to clean it up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently there is no API to uninitialize mdio. Add two APIs for this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In phy_connect_dev(), if the phy device has an accociated mac device
before, a warning message will be printed. But we should test the
old device against the new one, if they are actually the same one,
don't print the warning message.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In get_phy_device_by_mask(), when no phy is found, currently we only
print a message to show the first phy address that is not found. But
this is not always the case as multiple phys can be specified by
phy_mask. Change to print all phys that are not found, and to reduce
the console boot log, change to use 'debug' instead of 'printf'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In get_phy_device_by_mask(), when no phy is found, we should not
create any phy device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
NAND-tree is used to check wiring between MAC and PHY using NAND gates
on the PHY side, hence the name.
NAND-tree initial status is latched at reset by probing the IRQ pin.
However some devices are sharing the PHY IRQ pin with other peripherals
such as Atmel SAMA5D[34]x-EK boards when using the optional TM7000
display module, therefore they are switching the PHY in NAND-tree test
mode depending on the current IRQ line status at reset.
This patch ensure PHY is not in NAND-tree test mode only for the Micrel
KSZ8051 PHY used by Atmel. There are other Micrel PHY affected but I
doubt they are used on such weird hardware design.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Casting from dev->priv to pci_dev_t changes the value's size on a 64-bit
system. This causes the compiler to complain about casting a pointer to an
integer of a different (smaller) size. To avoid this, cast to an integer
of matching size first, then perform an int->int cast to perform the size
change. This signals explicitly that we do want to change the size, and
avoids the compiler warning. This is legitimate since we know the pointer
actually stores a small integer, not a pointer value.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The net_boot_file_name buffer is used as storage for the bootfilename
command line argument to network boot commands such as tftp and nfs.
Increase the size of this buffer to 1024 bytes as the current size of
128 bytes is restrictive for arbitrary paths on the server.
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds support for Micrel KSZ8021RNL & KSZ8031RNL.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Using NAKs on empty RX fifo for bulk in transfers is the right choice
for a interrupt driven model, but U-Boot uses polling and expects an
immediate answer if there is no incoming packet. Using ZLP Bulk In Response
(BIR) mode avoids unexpected timeouts in the host controller driver.
As ZLP mode is reset default, there is no need to set it.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If Option 52 in the vendor option field signals overloading
of the file and/or sname fields, these field may contain
additional options. Formatting of file/sname contained options
is the same as in the vendor options field, but without the
leading magic.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If 'file' is overloaded, it is wrong to get or put the bootfile name
from it/to it.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.
To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.
For the same reason, initrd_high is set to the value of 0xffffffff too.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1043ARDB Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G port
* QSGMII with 4x 1G ports
* Two RGMII ports
PCIe:
* PCIe2 (Lanes C) to mini-PCIe slot
* PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
codes related to phylib operations should be wrapped by CONFIG_PHYLIB.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
In convention, the '0' is a normal return value indicating there isn't
an error. While some functions of FMan IM driver treat '0' as an error
return value.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The FMan IM driver is developed for 32-bit platfroms and isn't
friendly to 64-bit platforms, so do the minimal refactor:
1. Refine the MURAM management and access.
2. Correct the initialization and operations for QDs and BDs.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The Frame Manager(FMan) is a big-endian peripheral, so the
registers, internal MURAM and BDs, which are allocated in main
memory and used to communication between core and FMan, should
be accessed in big-endian. The big-endian platforms can access
them directly as the code implemented so far, while for the
little-endian platforms it need to swap the byte-order.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
