Commit 8502fe84a4 ("configs: am57xx_evm: define
CONFIG_SPL_LOAD_FIT_ADDRESS for SPL-DFU") implements incorrect ifdef
logic, which leads to DFU variables absence in non-SPL environment. Fix
that in order to bring back DFU variables, by reflecting the logic in
include/configs/dra7xx_evm.h.
Fixes: 8502fe84a4 ("configs: am57xx_evm: define CONFIG_SPL_LOAD_F...")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
wkup_vtm populates only 1 power-domain cell in it's node. But the
power-domain cell are defined as 2. Due to this the following warning
comes during build:
arch/arm/dts/k3-am654-r5-base-board.dtb: Warning (power_domains_property):
/interconnect@100000/interconnect@28380000/interconnect@42040000/
wkup_vtm@42050000:power-domains: property size (8) too small for cell size 2
Fix this by updating the power-domain cells.
Fixes: cfa6bd549c ("arm: dts: k3-am654-r5-base-board: Add VTM node")
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
commit 29f7d05a34 ("dm: core: Move ofdata_to_platdata() call earlier")
introduces changes in the order of device_probe execution.
ofdata_to_platdata now comes before the probe function which resulted in
a deadlock and caused boot hang on AM6 devices.
Deadlock sequence: tps62360_regulator_ofdata_to_platdata --> i2c_get_chip
--> device_probe(tps62360) --> tps62360_regulator_ofdata_to_platdata
Hence convert ofdata_to_platdata to the missing probe function to fix the
hang.
Fixes: 22e8f18980 ("power: regulator: tps6236x: add support for tps6236x regulators")
Signed-off-by: Keerthy <j-keerthy@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On K3 systems U-Boot runs on both an R5 and a large ARM cores (usually
A53 or A72). The large ARMs are coherent with the DMA controllers and
the SYSFW that perform authentication. And previously the R5 core did
not enable caches. Now that R5 does enable caching we need to be sure
to clean out any of the image that may still only be in cache before we
read it using external DMA for authentication.
Although not expected to happen, it may be possible that the data was
read back into cache after the flush but before the external operation,
in this case we must invalidate our stale local cached version.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Not finding a node that we try to disable does not always need to be
fatal to boot but should at least print out a warning. Return error
from fdt_disable_node as it did fail to disable the node, but only
warn in the case of disabling the TRNG as this will not prevent boot.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Sync new additions to non-HS defconfig with HS defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Sync new additions to non-HS defconfig with HS defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Make the wkup_i2c0 module usable across all stages of U-Boot by adding
the needed definitions including the associated pinmux definitions.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The TI J721E EVM system on module (SOM), the common processor board, and
the associated daughtercards have on-board I2C-based EEPROMs containing
board config data. Use the board detection infrastructure to do the
following:
1) Parse the J721E SOM EEPROM and populate items like board name, board
HW and SW revision as well as board serial number into the TI common
EEPROM data structure residing in SRAM scratch space
2) Check for presence of daughter card(s) by probing associated I2C
addresses used for on-board EEPROMs containing daughter card-specific
data. If such a card is found, parse the EEPROM data such as for
additional Ethernet MAC addresses and populate those into U-Boot
accordingly
3) Dynamically apply daughter card DTB overlays to the U-Boot (proper)
DTB during SPL execution
4) Dynamically create an U-Boot ENV variable called name_overlays
during U-Boot execution containing a list of daugherboard-specific
DTB overlays based on daughercards found to be used during Kernel
boot.
This patch adds support for the J721E system on module boards containing
the actual SoC ("J721EX-PM2-SOM", accessed via CONFIG_EEPROM_CHIP_ADDRESS),
the common processor board ("J7X-BASE-CPB"), the Quad-Port Ethernet
Expansion Board ("J7X-VSC8514-ETH"), the infotainment board
("J7X-INFOTAN-EXP") as well as for the gateway/Ethernet switch/industrial
expansion board ("J7X-GESI-EXP").
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use dm_i2c_probe() rather than i2c_get_chip() when trying to access
board-detection EEPROM devices. This has the advantage of more gracefully
handling the case when the EEPROM is not present by allowing to exit the
function early rather than failing and outputting an error message on the
I2C transactions that follow.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Adding the configurations to the evm_defconfig file
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
BeagleBoard.org BeagleBone AI is an open source hardware single board
computer based on the Texas Instruments AM5729 SoC featuring dual-core
1.5GHz Arm Cortex-A15 processor, dual-core C66 digital signal
processor (DSP), quad-core embedded vision engine (EVE), Arm Cortex-M4
processors, dual programmable realtime unit industrial control
subsystems and more. The board features 1GB DDR3L, USB3.0 Type-C, USB
HS Type-A, microHDMI, 16GB eMMC flash, 1G Ethernet, 802.11ac 2/5GHz,
Bluetooth, and BeagleBone expansion headers.
For more information, refer to:
https://beaglebone.ai
The corresponding patch against the mainline linux kernel can be found
at: https://patchwork.kernel.org/patch/11254903/
This patch introduces the BeagleBone AI device tree.
Note that the device use the "ti,tpd12s016" component which is software
compatible with "ti,tpd12s015". Thus we only use the latter driver.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
These are necessities for beaglebone ai boot. There is the addition of
CONFIG_SUPPORT_EMMC_CONFIG to the Kconfig file. This is present upstream
but not in 19.01 yet.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This patch configures the pinmux settings for the BeagleBone AI after
the emmc read has completed.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
BeagleBoard.org BeagleBone AI rev A1 does not include a board
identifier I2C EEPROM due to a design oversight. These boards have
been put into production and are generally available now.
The board identifier information, however, has been included in the
second eMMC linear boot partition (/dev/mmcblk1boot1).
This patch works by:
* First, looking for a board identifier I2C EEPROM and if not found,
* Then seeing if the boot mode matches BeagleBone AI with eMMC in the
boot chain to make sure we don't enable eMMC pinmuxes on boards
that don't support it, and
* Finally, initializes the eMMC pins and reading the header.
Signed-off-by: Jason Kridner <jdk@ti.com>
Signed-off-by: Caleb Robey <c-robey@ti.com>
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add Support for writing to PHY registers for J721e. There are number of
differences between the J721e 8 bit PHY, J721e 4 bit PHY and AM654 PHY.
Create a driver_data structure with an ops and flags field and use the
flags field to indicate these differences. The differences are as
follows:
1. The J721e 4 bit instance PHY does not have a DLL. Introduce a
DLL_PRESENT flag to make sure that DLL related registers are accessed
only where they are present. Also add a separate set_ios_post()
callback.
2. The J721e 8 bit instance is not muxed with anything else inside the
SoC and hence the IOMUX_ENABLE filed does not exist. Add a flag which is
used to indicate the presence of this field.
3. The register field used to select DLL frequency is 3 bit wide in
J721e as compared to 2 bits in AM65x. Add another flag that
distinguishes these fields.
4. The strobe select field is 8 bit wide as compared to 4 bit wide for
AM65x. Add yet another flag to indicate this difference. Strobe select
is used only for HS400 speed mode, support for which has not been added
in AM65x.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Get clk_xin by name instead of by index to avoid having to put clocks in
the same order in all devices.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Cast pointers properly so as to avoid warnings when driver is built for
32 bit platforms
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
UDMA always expects 64 bit address pointer of the transfer descriptor in
the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size.
Therefore copy over 32 bit pointer value to 64 bit variable before
pushing it over to the ring, so that upper 32 bits are 0s.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Exposed ring mode works well with 32 bit and 64 bit cores without need
for Proxies for 32 bit cores. Therefore switch to exposed ring mode.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Fix up the debug prints that were dumping state of TCHAN RT registers to
use tchan for MEM_TO_DEV transfers.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Remove redundant coherency checks before calling cache ops in UDMA
driver. This is now handled in arch specific cache operation
implementation based on Kconfig option
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Instead of looking getting reference to SYSFW device using name which
is not guaranteed to be constant, use phandle supplied in the DT node to
get reference to SYSFW
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Flush caches when pushing an element to ring and invalidate caches when
popping an element from ring in Exposed Ring mode. Otherwise DMA
transfers don't work properly in R5 SPL (with caches enabled) where the
core is not in coherency domain.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}())
and their dependencies from Linux. These are required for upcoming DMA
resource allocation support for TI's K3 SoCs.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Currently, the da850-lcdk uses SPL_OF_PLATDATA and manually loads
the necessary source code instead of using the auto-generated,
because the drivers don't properly autogenerate the code.
This patch simply enables the various device tree options to
mimic the da850-evm which doesn't need or use OF_PLATDATA for
device tree support. It does not disable OF_PLATDATA.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to
be indexed into a lookup table to get the actual temperature. Fix the
naming and datatype of the adc value variable.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
J721e has two instances of Cadence USB3 controller. Add DT nodes for the
same. USB0 is configured to device mode and USB1 is configured to host
mode. For now only high speed mode is supported.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit add to u-boot the support to decrypt
fit image encrypted with aes. The FIT image contains
the key name and the IV name. Then u-boot look for
the key and IV in his device tree and decrypt images
before moving to the next stage.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
This commit add the support of encrypting image with aes
in mkimage. To enable the ciphering, a node cipher with
a reference to a key and IV (Initialization Vector) must
be added to the its file. Then mkimage add the encrypted
image to the FIT and add the key and IV to the u-boot
device tree.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
This commit add test unit for aes196 and aes256.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Until now, we only support aes128. This commit add the support
of aes192 and aes256.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the code, we use the size of the key for the
size of the block. It's true when the key is 128 bits,
but it become false for key of 192 bits and 256 bits.
So to prepare the support of aes192 and 256,
we introduce a constant for the iaes block size.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Clearfog: Fix SD booting (Baruch)
- Misc updates to MMC handling in SPL to support booting from
main data partition (vs hardware boot partition) on MVEBU (Baruch)
