Commit graph

7 commits

Author SHA1 Message Date
Icenowy Zheng
c199489f17 sunxi: add basic V3s support
Basic U-Boot support is now present for V3s.

Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.

As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-21 09:23:17 +02:00
Chen-Yu Tsai
379febac5a sunxi: Add initial support for R40
The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.

The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.

The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:00 +02:00
Andre Przywara
997bde6038 sunxi: introduce Allwinner H5 config option
The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
As the peripherals and the pinmuxing are almost identical, we piggy
back on the shared MACH_SUN8I_H3_H5 config symbol.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05 15:03:17 +05:30
Icenowy Zheng
65d2d4f239 sunxi: fix SID read on H3
H3 SID controller has some bug, which makes the initial SID value at
SUNXI_SID_BASE wrong when boot.

Change the SID retrieve code to call the SID Controller directly on H3,
which can get the correct value, and also fix the SID value at
SUNXI_SID_BASE, so that it can be used by further operations.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-20 16:08:50 +01:00
Siarhei Siamashka
d96ebc468d sunxi: Add support for Allwinner A64 SoCs
The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.

Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:28 +02:00
Alexander Graf
0ea5a04fbc sunxi: Explicitly cast u32 pointer conversions
Some parts of the sunxi code cast explicitly between u32 values and pointers.
This is not a problem in practice, because all 64bit SoCs today only use the
lower 32 bits for their phyical address space. But we need to make sure that
the compiler is sure this is not an accident as well.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:28 +02:00
Alexander Graf
e6e505b93c sunxi: Move cpu independent code to mach directory
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while
most of it is just generic code that could as well be used on an AArch64 SoC.

Move all files that are not really tied to armv7 into a new mach-sunxi
directory.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-04-01 09:52:28 +02:00
Renamed from arch/arm/cpu/armv7/sunxi/cpu_info.c (Browse further)