This magic constant with zero documentation, when it's last 8 bits are set to
0x45, configures correctly the PERCLK dividers. Therefore the I2C operates
correctly when divider computed from PERCLK.
Note: This constant is written to CBCDR register in
arch/arm/cpu/armv7/mx5/lowlevel_init.S, but it's written only once. The register
is accessed three more times in the file, with different values written to it
each time.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
CONFIG_L2_OFF is obsolete after the following commit:
e47f2db537
armv7: rename cache related CONFIG flags
Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:
CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF
Since imx5 does not provide L2 cache operations(Enable/Disable)
Simply remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:
CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF
Signed-off-by: Aneesh V <aneesh@ti.com>
V2:
* Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
V4:
* Changed all three flags to the final names suggested as above
and accordingly changed the commit message
The following boards gain device tree support with this patch:
ca9x4_ct_vxp - Versatile Express
i.mx5 boards:
efikamx
mx51evk
mx53evk
OMAP boards:
devkit8000
igep0020
igep0030
omap3_overo
omap3_pandora
omap4_sdp3430
omap3_zoom1
omap3_zoom2
omap4_panda
omap4_sdp4430
Tegra boards:
Harmony
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Supported:
MMC
IDE
PMIC
SPI flash
LEDs
I can boot the kernel supplied by freescale/genesi with this from MMC card
and/or PATA disk.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
