Commit graph

57 commits

Author SHA1 Message Date
Kim Phillips
5be58f5fc8 powerpc/85xx: configure autocompletion support
because it's convenient.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-01 11:18:44 -05:00
Kumar Gala
99d9c07edc powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:37:11 -05:00
Becky Bruce
199e262eb3 mpc85xx: Add reginfo command
The new command dumps the TLBCAM, the LAWs, and the BR/OR regs.
Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Heiko Schocher
4b142febff common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-12-08 22:14:07 +01:00
Becky Bruce
af860962b5 85xx: Remove unused CONFIG_ASSUME_AMD_FLASH from config files
A bunch of the 85xx boards have this cruft in them - it's not used
anywhere.  Delete it.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
2009-12-02 22:57:16 +01:00
Kumar Gala
f90dc43fd6 85xx: Removed BEDBUG support from FSL 85xx boards
For some reason the MPC8544 enabled BEDBUG if PCI was enabled and that
got copied int the MPC8536, MPC8572 and P2020 DS boards.  The BEDBUG
support has never been made to work completely on e500/85xx so we
just disable it to save space and match the other FSL 85xx boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-10 16:40:55 -05:00
Roy Zang
f6155c6fbb 85xx: Add pci/pcie E1000 ethernet support for MPC8544DS and MPC8536 boards
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-22 09:43:47 -05:00
Kumar Gala
6bb5b41229 85xx: Report which "bank" of NOR flash we are booting from on FSL boards
The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
swizzling the upper address bits of the NOR flash we boot out of which
creates the concept of "virtual" banks.  This is useful in that we can
flash a test of image of u-boot and reset to one of the virtual banks
while still maintaining a working image in "bank 0".

The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-22 09:42:22 -05:00
Kumar Gala
89188a6233 85xx: Bump up the BOOTMAP to 16M on FSL 85xx boards
We have always mapped at least 16M in the kernel and we have seen cases
with new kernel features that a kernel image needs more than 8M of
memory.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-21 09:02:40 -05:00
Timur Tabi
890d242fac remove _IO_BASE and KSEG1ADDR from board configuration files
The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet
driver, but the code that used that macro was removed over a year
ago, so board configuration files no longer need to define it.

The _IO_BASE macro is also automatically defined to 0 if it isn't
already set, so there's no need to define that macro either in the
board configuration files.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2009-07-11 00:19:16 +02:00
Kumar Gala
aca5f018a8 85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boards
Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
5af0fdd81c 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards
Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
5f91ef6acd 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-23 17:03:13 -06:00
Kumar Gala
10795f42cb 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Peter Tyser
ba490b7761 Remove unused CONFIG_ADDR_STREAMING defines
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-14 12:42:42 +01:00
Jon Loeliger
5a105a333d Removed unused CONFIG_L1_INIT_RAM symbol.
Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-03 22:48:32 -06:00
Dave Liu
9b0ad1b1c7 85xx: remove the unused ddr_enable_ecc in the board file
The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-03 22:44:48 -06:00
Kumar Gala
2dba0dea98 85xx: Convert all fsl_pci_init users to new APIs
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:35:12 -05:00
Kumar Gala
0151cbaccf 85xx: Enable 64-bit PCI resources on all Freescale boards
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:33:06 -05:00
Liu Yu
bff188baf9 Make pixis_set_sgmii more general to support MPC85xx boards.
The pixis sgmii command depend on the FPGA support on the board, some 85xx
boards support SGMII riser card but did not support this command, define
CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command.

Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits
are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and
PIXIS_VCFGEN1_MASK in header file for both boards.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
2008-10-18 21:54:07 +02:00
Kumar Gala
1c9aa76bf9 85xx: Enable interrupt and setexpr commands on Freescale 85xx boards
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-18 21:54:04 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Jean-Christophe PLAGNIOL-VILLARD
0e8d158664 rename CFG_ENV macros to CONFIG_ENV
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:48:06 +02:00
Jean-Christophe PLAGNIOL-VILLARD
5a1aceb068 rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASH
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:48:04 +02:00
Andy Fleming
5a8a163ac3 Add pixis_set_sgmii command
The 8544DS and 8572DS platforms support an optional SGMII riser card to
expose ethernet over an SGMII interface.  Once the card is in, it is also
necessary to configure the board such that it uses the card, rather than
the on-board ethernet ports.  This can either be done by flipping dip switches
on the motherboard, or by modifying registers in the pixis.  Either way
requires a reboot.

This adds a command to allow users to choose which ports are routed through
the SGMII card, and which through the onboard ports.  It also allows users
to revert to the current switch settings.

This code does not work on the 8572, as the PIXIS is different.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:15 -07:00
Andy Fleming
652f7c2eef Add support for Freescale SGMII Riser Card
The 8544DS and 8572DS systems have an optional SGMII riser card which
exposes new ethernet ports which are connected to the eTSECs via an
SGMII interface.  The SGMII PHYs for this board are offset from the standard
PHY addresses, so this code modifies the passed in tsec_info structure to
use the SGMII PHYs on the card, instead.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:15 -07:00
Kumar Gala
1167a2fd56 FSL DDR: Convert MPC8544DS to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:50 -05:00
Jean-Christophe PLAGNIOL-VILLARD
00b1883a4c drivers/mtd: Move conditional compilation to Makefile
rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-13 01:40:42 +02:00
Andy Fleming
1107014e83 Clean up INIT_RAM options
The L2_INIT_RAM option was unused, and recent changes to the TLB code
meant that the INIT_RAM TLBs weren't being cleared out.  In order to reduce
the amount of mapped space attached to nothing, we change things so the TLBs
get cleared.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-07-14 20:29:07 -05:00
Andy Fleming
4524561820 Remove fake flash bank from 8544 DS
The fake flash bank was generating errors for anyone who didn't have a
PromJET hooked up to the board.  As that constitutes the vast majority of
users, we remove it.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-07-14 20:26:57 -05:00
Kumar Gala
630d9bfcb5 MPC8544DS: Add ATI Video card support
Add support for using a PCIe ATI Video card on PCIe2.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-14 20:21:11 -05:00
Andy Fleming
ab5cda9f88 Remove LBC_CACHE_BASE from 8544 DS
The 8544 DS doesn't have any cacheable Local Bus memories set up.  By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-07-14 11:21:33 -05:00
Kumar Gala
ddde74a159 85xx: remove dummy board_early_init_f
A number of board ports have empty version of board_early_init_f
for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-11 00:36:02 -05:00
Kumar Gala
81e56e9af0 MPC8544DS: Update config.h
* Enable flash progress
* remove CLEAR_LAW0 since we dont really use it

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-11 00:35:57 -05:00
Kumar Gala
978e81604c 85xx: Remove unused and unconfigured memory test code.
Remove unused and unconfigured DDR test code from FSL 85xx boards.
Besides, other common code exists.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-11 00:35:52 -05:00
Roy Zang
292188e155 MPC8544DS: Removes the unknown flash message information
This patch removes the unknown flash message information:
'## Unknown FLASH on Bank 1 - Size = 0xdeadbeef = -286261248 MB'
This unknown flash message is caused by PromJet.
Some of the board user is unhappy with this information.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-26 00:22:59 +02:00
Kumar Gala
f69766e4b5 85xx: Add the concept of CFG_CCSRBAR_PHYS
When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:03 -05:00
Kumar Gala
7dc358bb0d 85xx: Get ride of old TLB setup code
Now that all boards have been converted, remove old config code and the
config option for the new style.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:19:18 -06:00
Kumar Gala
0f7a3dc95c 85xx: Convert MPC8544 DS to new TLB setup
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:05:35 -06:00
Kumar Gala
4bcae9c92a 85xx: convert MPC8544 DS over to use new LAW init code
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-16 23:21:55 -06:00
Kumar Gala
b009f3eca9 85xx: Remove cache config from configs.h
Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.

Also, minor cleanup in cache.h to make the code a bit more readable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-09 16:25:04 -06:00
Kumar Gala
8ff3de61fc Handle MPC85xx PCIe reset errata (PCI-Ex 38)
On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Kumar Gala
82ac8c9714 Update Freescale MPC85xx ADS/CDS/MDS board config
* Enabled CONFIG_CMD_ELF

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Kumar Gala
50c03c8cf4 Update MPC8544 DS config
* Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2
* Removed some misc environment setup
* Moved to using fdtfile & fdtaddr as fdt env var names
* Enabled CONFIG_CMDLINE_EDITING

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:19 -06:00
Kumar Gala
addce57e2e Update MPC8544DS to use libfdt
Updated the MPC8544DS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:19 -06:00
Jason Jin
db74b3c1c9 Unify pixis_reset altbank across board families
Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-11-17 00:57:51 +01:00
Kumar Gala
56a9270521 Fix ULI RTC support on MPC8544 DS
The RTC on the M1575 ULI chipset requires a dummy read before
we are able to talk to the RTC.  We accomplish this by adding a
second memory region to the PHB the ULI is on and read from it.

The second region is added to maintain compatiabilty with Linux's
view of the PCI memory map.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-04 16:00:48 -05:00
Kim Phillips
7608d75f9c support board vendor-common makefiles
if a board/$(VENDOR)/common/Makefile exists, build it.

also add the first such case, board/freescale/common/Makefile, to
handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
dictated by board configuration.

thusly get rid of alternate build dir errors such as:

FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory

by putting the common/ mkdir command in its proper place (the common
Makefile). Common bits from existing individual board Makefiles have
been removed.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-29 02:15:46 +02:00
Kim Phillips
3bb342fc85 fdt: remove unused OF_FLAT_TREE_MAX_SIZE references
and make some minor corrections to the FDT part of the README.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-29 01:46:25 +02:00
Kumar Gala
d64ee908a1 Update MPC8544 DS PCI memory map
The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.

So make it use far less IO & memory space and have it use the shared LAW.  This
free's up a LAW for PCIe1 IO space.  Also reduce the amount of IO space needed
by each bus.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-08-16 16:18:45 -05:00