CONFIG_SYS_LOAD_ADDR is absolutely safe to store image for
fastboot.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in
config_distro_defaults.h, and we don't need them in SPL stage.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to
setup sdmmc gpio, otherwise we will hit an error below:
=>mmc info
blk_get_device: if_type=6, devnum=0: dwmmc@ff0c0000.blk, 6, 0
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
- -1 -1
- -1 0
- found
uclass_find_device_by_seq: 0 1
- -1 -1
- -1 0
- not found
fdtdec_get_int_array: interrupts
get_prop_check_min_len: interrupts
Buswidth = 1, clock: 0
Buswidth = 1, clock: 400000
Sending CMD0
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
This reverts commit 6efeeea79c.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Add an extra byte so that this data is not byteswapped.
Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers. In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.
Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed. The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
RK3399 needs reserve 0x200000 at the beginning of DRAM, for ATF bl31.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now,
remove them.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Not like the mmc-legacy which the devnum starts from 1, it starts from 0
in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num().
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This patch is style-related only, to reformat all the start.S code,
actually not following a coherent style inside single files and
between different cpu start.S files.
Linux format has been respected, as
- max line width at 80 columns
- one 8 cols tab between asm instructions and operands
- inline comments, where any, fixed at col 41
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
connected to TI QSPI over CS0. Hence, add QSPI and flash slave
DT nodes.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable
CONFIG_SPI_FLASH_BAR to access flash regions above 16MB.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
Therefore update the spi-max-frequency value of QSPI node for DRA74 and
DRA72 evm. This increase flash read speed by ~2MB/s.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Now that QSPI driver can support 76.8MHz, update the
CONFIG_SF_DEFAULT_SPEED to the same value.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
As per commit b545a98f5d ("spi: ti_qspi: Add delay
for successful bulk erase) says its added to meet bulk erase timing
constraints. But bulk erase is a cmd to flash and delay in read path
does not make sense. Morever, testing on DRA74/DRA72 evm has shown that
this delay is no longer required.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value
QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in
ti_qspi_cs_deactivate(). Therefore CS is never deactivated between
successive READ ID which results in sf probe to fail.
Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Pass the board/freescale/*mx*/ path as files maintained by Stefano
Babic.
While this is not ideal and does not cover all the i.MX board cases,
it gives at least a better hint for the /scripts/get_maintainer.pl
tool.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize
the generic timer on all CPU's. This allows to make use of the timer
freuquency register also on other CPU than the start CPU which is
important for KVM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.
Remove the unneeded definition.
Cc: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
novena uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.
Remove the unneeded definition.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Marek Vasut <marex@denx.de>
imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Cc: Martin Donnelly <martin.donnelly@ge.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Heiko Schocher <hs@denx.de>
imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Currently it's recommended to move some configuration options to the
defconfig file.
Move some USB related options to the defconfig file.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
This commit adds support for the Toradex Computer on Modules
Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence
can be easily supported by one board. The board code detects RAM
size at runtime which is one of the differences between the two
boards. The board also uses the UART's in DTE mode, hence making
use of the new DTE support via serial DM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
It's not necessary to use the is_cpu_type function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Added removal of the fsl,ext-reset-output property in the wdog node for board
revisions that pre-date the addition of the external watchdog reset signal.
This property is a recent addition to mainline linux kernel in order to
specify that the IMX watchdog external reset should be used instead of the
internal chip-level reset.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Re-factor the board-specific dt fixups so that they are easier to follow
and extend in the future:
- use defines for DT paths
- use switch/case per board
- order models numerically
There is no functional change in the code
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The hwconfig env var allows user to control hardware specific configuration
of board specific features but not all Ventana boards have the same features.
We will use the magic default value of "_UNKNOWN_" to signify that the
bootloader should create this based on detected board model.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3b1f681131 caused a regression that removes
board info dispaly for Gateworks Ventana boards because it made the invalid
assumption that CONFIG_DISPLAY_BOARDINFO_LATE was the same thing as
CONFIG_DISPLAY_BOARDINFO.
Ventana needs to call show_board_info in late init because we need to have
the i2c eeprom based model info. Re-define CONFIG_DISPLAY_BOARDINFO_LATE
to allow that to happen.
Cc: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The IMX6 PCIe host controller does not have a proper reset and as such there
are several issues that can arise if PCI is enabled in the bootloader follwed
by Linux trying to re-configure LTSSM and/or toggling PERST# to the devices.
For now, the best approach seems to default to disabling PCI by defaulting
pciedisable=1. This can be overridden by the user if they need PCI in the
bootloader, for example:
- GW552x needing ethernet access in bootloader
- GW16082 expansion board needing a device-tree fixup for irq mapping
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Ventana boards with a PCI Marvell Sky2 GigE MAC require the MAC address to
be placed in a DT node in order for the mainline linux driver to obtain it.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW16082 mini-PCI expansion mezzanine uses a TI XIO2001 PCIe-to-PCI
bridge with legacy INTA/B/C/D interrupts. These interrupts are assigned
in the reverse order according to the PCI spec.
If the TI bridge is found on the Ventana PCI bus, add device-tree nodes
according to bus enumeration explicitly defining the interrupt mapping
to override the default PCI mapping in the Linux kernel. This allows
the GW16082 to work with upstream kernels that support device-tree
irq parsing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
