Commit graph

254 commits

Author SHA1 Message Date
Tom Rini
fe9822556e Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2016-12-12 07:18:53 -05:00
Masahiro Yamada
996fcdadba ARM: uniphier: remove unneeded parentheses
Just a cosmetic cleanup.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-10 01:42:51 +09:00
Masahiro Yamada
82ff6c392f ARM: uniphier: remove unneeded initializer
This will be used to store the return value of readl().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-10 01:42:51 +09:00
Simon Glass
dd38045dce spl: uniphier: Drop spl_board_announce_boot_device()
This function is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:17 -05:00
Simon Glass
ebc4ef61d7 spl: Add a name to the SPL load-image methods
It is useful to name each method so that we can print out this name when
using the method. Currently this happens using a separate function. In
preparation for unifying this, add a name to each method.

The name is only available if we have libcommon support (i.e can use
printf()).

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:13 -05:00
Masahiro Yamada
6eeb624148 ARM: uniphier: update DRAM init code for LD11 SoC
Introduce run-time DDR PHY training.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:24:30 +09:00
Masahiro Yamada
5f49845ecc ARM: uniphier: support DDR PHY parameter dump command for LD11
Add the LD11 SoC data and adjuts the printf() format because this is
a 64-bit SoC.  Otherwise, 16-digits pointer addresses would break
the log format.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:24:30 +09:00
Masahiro Yamada
adf55f63ae ARM: uniphier: refactor DDR PHY parameter dump command
Do not hard-code the number of DX blocks because it is a different
value for LD11 SoC.

Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it
is the last user.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:24:30 +09:00
Masahiro Yamada
6dd34ae4c4 ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoC
The DDR PHY register view of LD11 is slightly different from that
of LD4/Pro4/sLD8, but it will be possible to share the register
macros (and I want to re-use as much code as possible).  Change
the code in the more flexible form.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:24:30 +09:00
Masahiro Yamada
9c5313dc09 ARM: uniphier: do not run harmful code for USB boot mode of LD11 ES3
The USB boot without the stand-by MPU is available on ES3 or later
of LD11 SoC, but the code in this if-conditional block must not be
run when booting from USB.  Check if the boot device is USB, and
skip the code in the case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:24:30 +09:00
Masahiro Yamada
76466bd7be ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabled
At the moment, the clk driver is not clever enough to automatically
enable parent clocks like Linux.  Enable the STDMAC clock explicitly
if USB is enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:24:30 +09:00
Masahiro Yamada
a8b66ac87c ARM: uniphier: fix DRAM init poll address for LD4, Pro4, sLD8
The status register should be polled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:24:30 +09:00
Masahiro Yamada
efaa22e426 ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.h
This PHY might be used for other SoCs in the future.
Avoid including the SoC name in the header name.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:24:30 +09:00
Masahiro Yamada
b8909976ed ARM: uniphier: update DRAM init code for LD20 SoC (3rd)
- Constify UMC setting data arrays
  - Merge data arrays *_d0 and *_d1.
  - Add PHY parameters for LD20 C1 board

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:24:26 +09:00
Masahiro Yamada
da0d4d1380 ARM: uniphier: remove unused board attribute macros
After SoC evaluation, they turned out unnecessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:01:40 +09:00
Masahiro Yamada
295326231d ARM: uniphier: enable SSC for more PLLs for LD20 SoC
For Electro-Magnetic Compatibility.

Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:01:40 +09:00
Masahiro Yamada
dd39ee8a54 ARM: uniphier: remove unneeded mdelay() in PLL setting function
This delay is already cared by the callers of this function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:01:40 +09:00
Masahiro Yamada
40749d5a83 ARM: uniphier: adjust fdt_file environment handling to latest Linux
The environment fdt_file is useful to remember the appropriate DTB
file name.  Adjust it to the recent renaming in the upstream kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29 17:01:40 +09:00
Masahiro Yamada
70dda1b1e8 ARM: uniphier: remove unnecessary EHCI reset deassertion
It is now deasserted by the reset controller driver.  Drop the
ad-hoc code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-18 14:27:13 +09:00
Masahiro Yamada
52159d27ff ARM: dts: uniphier: sync DT with latest Linux
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-18 14:06:46 +09:00
Masahiro Yamada
0bd203bbd1 ARM: uniphier: fix addresses of Cortex-A72 gear setting macros
My mistake during copy-paste work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-18 14:06:46 +09:00
Simon Glass
b02e4044ff libfdt: Bring in upstream stringlist functions
These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.

This applies the following upstream commits by
Thierry Reding <treding@nvidia.com> :

   604e61e fdt: Add functions to retrieve strings
   8702bd1 fdt: Add a function to get the index of a string
   2218387 fdt: Add a function to count strings

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-13 13:54:10 -06:00
Masahiro Yamada
66e3efebbc ARM: uniphier: insert udelay() just before support_card_reset_deassert()
As for LD11/LD20, we can no longer rely on the udelay() in the PLL
init functions.  udelay(200) is needed here to keep the ethernet
device in the reset state for enough time.  Anyway, 200 usec is
quite short for humans, so nobody cares it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10 10:03:23 +09:00
Masahiro Yamada
baaafaaad3 ARM: uniphier: add work-around for VBO noise problem
Raise the VDD09 voltage line to 1.0V to suppress VBO noise.
This errata work-around code is needed only for ES1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10 10:03:23 +09:00
Masahiro Yamada
c89638a027 ARM: uniphier: update DRAM init code for LD20 SoC (2nd)
- Do not reference CONFIG_DDR_FREQ; now the DDR frequency
    is passed from the uniphier_board_data structure
  - Constify parameter arrays
  - Tidy up cluttered macros
  - Lots of code cleanups
  - Lots of coding style fixes

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10 10:03:23 +09:00
Masahiro Yamada
6c22742d3d ARM: uniphier: enable SSC for DPLL (DRAM PLL) on LD11 SoC
For Electro-Magnetic Compatibility test.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10 10:03:23 +09:00
Masahiro Yamada
dacdb24027 ARM: uniphier: do not setup pins for System Bus on NAND boot mode
For LD11 and LD20 SoCs, the System Bus and NAND are multiplexed
in the same I/O pins.  When booting from a NAND device, pin-mux
for the System Bus must not be set-up because they are exclusive
with each other.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10 10:03:23 +09:00
Simon Glass
2a2ee2ac35 spl: Pass spl_image as a parameter to load_image() methods
Rather than having a global variable, pass the spl_image as a parameter.
This avoids BSS use, and makes it clearer what the function is actually
doing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06 15:08:52 -04:00
Simon Glass
97d9df0a91 spl: Convert spl_board_load_image() to use linker list
Add a linker list declaration for this method and remove the explicit
switch() code. Update existing users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06 15:08:50 -04:00
Simon Glass
ecdfd69a4b spl: Convert boot_device into a struct
At present some spl_xxx_load_image() functions take a parameter and some
don't. Of those that do, most take an integer but one takes a string.

Convert this parameter into a struct so that we can pass all functions the
same thing. This will allow us to use a common function signature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06 14:53:36 -04:00
Simon Glass
71316c1d8c spl: Add a parameter to spl_parse_image_header()
Instead of using the global spl_image variable, pass the required struct in
as an argument.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06 14:48:17 -04:00
Masahiro Yamada
c72f4d4c2e ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
   SPL memory footprint)
 - Adjust CPLL/MPLL to the final tape-out frequency
 - Set the Cortex-A53 clock to the maximum frequency since it is
   running at 500MHz (SPLL/4) on startup

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-23 01:00:23 +09:00
Masahiro Yamada
0298f4c003 ARM: uniphier: move CONFIG_SPL_* to defconfig or select
As I repeated in the ML, I am unhappy with config entries with bare
defaults.  Kick them out of arch/arm/mach-uniphier/Kconfig.

Currently, CONFIG_SPL_SERIAL_SUPPORT is not user-configurable
(build fails without it), but it should be fixed later anyway,
so I am moving CONFIG_SPL_SERIAL_SUPPORT to defconfigs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-23 00:38:38 +09:00
Tom Rini
9a6535e05f Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2016-09-18 14:05:30 -04:00
Masahiro Yamada
f9d7e17e84 ARM: uniphier: update DRAM init code for LD20 SoC
Import the latest version from the Diag software.

  - Support LD21 SoC (including DDR chips in the package)
  - Per-board granule adjustment for both reference and TV boards
  - Misc cleanups

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:12:26 +09:00
Masahiro Yamada
682e09ff9f ARM: uniphier: add PLL init code for LD20 SoC
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper.  Split the common code into pll-base-ld20.c for easier
re-use.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:12:26 +09:00
Masahiro Yamada
fcc238baee ARM: uniphier: collect clock/PLL init code into a single directory
Now PLLs for DRAM controller are initialized in SPL, and the others
in U-Boot proper.  Setting up all of them in a single directory will
be helpful when we want to share code between SPL and U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:06:47 +09:00
Masahiro Yamada
6a3e4274e4 ARM: uniphier: move PLL init code to U-Boot proper where possible
The PLL for the DRAM interface must be initialized in SPL, but the
others can be delayed until U-Boot proper.  Move them from SPL to
U-Boot proper to save the precious SPL memory footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:06:44 +09:00
Masahiro Yamada
22de6b3374 ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PER
Basically, this should not be configured by users.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:47:27 +09:00
Masahiro Yamada
b78ffc53c5 ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20
This is the last code in the mach-uniphier/pinctrl/ directory.
Push the remaining code out to delete the directory entirely.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:47:27 +09:00
Masahiro Yamada
68557ec37e ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20
Use the pin-mux data in the pinctrl drivers by directly calling
pinctrl_generic_set_state().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:47:18 +09:00
Masahiro Yamada
5ac9dfbe9d ARM: uniphier: consolidate NAND pin-mux settings
The NAND subsystem has not supported the Driver Model yet, but the
NAND pin-mux data are already in the pinctrl drivers.  Use them by
calling pinctrl_generic_set_state() directly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:44 +09:00
Masahiro Yamada
6a93478b93 ARM: uniphier: remove ad-hoc pin-mux code for sLD3
These settings are nicely cared by the pinctrl driver now.  Remove.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:37 +09:00
Masahiro Yamada
cd477c9def ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoC
This is enabled by default for all the supported boot modes.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:36 +09:00
Simon Glass
e00f76cee9 Convert CONFIG_SPL_SERIAL_SUPPORT to Kconfig
Move this option to Kconfig and tidy up existing uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:19 -04:00
Simon Glass
d6b9bd8923 Convert CONFIG_SPL_NAND_SUPPORT to Kconfig
Move this option to Kconfig and tidy up existing uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:14 -04:00
Simon Glass
1fdf7c64ed Convert CONFIG_SPL_MMC_SUPPORT to Kconfig
Move this option to Kconfig and tidy up existing uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:13 -04:00
Simon Glass
cc4288ef42 Convert CONFIG_SPL_LIBGENERIC_SUPPORT to Kconfig
Move this option to Kconfig and tidy up existing uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:12 -04:00
Simon Glass
77d2f7f507 Convert CONFIG_SPL_LIBCOMMON_SUPPORT to Kconfig
Move this option to Kconfig and tidy up existing uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:11 -04:00
Masahiro Yamada
f6bbec3d5c ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21
Unfortunately, this SoC needs per-board adjustment between clock
and address/command lines.  This flag will be passed to the DRAM
init function and used for compensating the difference of DRAM
timing parameters.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-17 01:29:44 +09:00