Commit graph

7 commits

Author SHA1 Message Date
Jon Loeliger
cfc7a7f5bb cpu/86xx fixes.
Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.

Include MSSSR0 in error message.

Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-10 11:02:32 -05:00
Haiying Wang
9964a4dd0d Set Rev 2.x 86xx PIC in mixed mode.
Prevent false interrupt from hanging Linux as MSR[EE] is set
to enable interrupts by changing the PIC out of the default
pass through mode into mixed mode.

Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-03-22 11:02:35 -05:00
Jon Loeliger
3dfa9cfdce Use generic I2C register block on 85xx and 86xx.
Replace private IMMAP I2C structures with generic reg block
and allow 86xx to have multiple I2C device busses.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-10-20 17:16:35 -05:00
Jon Loeliger
8b283dbb3a Fix whitespace issues. 2006-10-10 17:16:04 -05:00
Jin Zhengxiong-R64188
fa7db9c377 Enable PCIE1 for MPC8641HPCN board
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2006-06-27 09:17:59 -05:00
Jon Loeliger
586d1d5abd Update 86xx address map and LAWBARs. 2006-05-19 13:54:02 -05:00
Jon Loeliger
debb7354d1 Initial support for MPC8641 HPCN board. 2006-04-26 17:58:56 -05:00