Commit graph

39782 commits

Author SHA1 Message Date
Simon Glass
f66153be19 buildman: Fix repeating board list with -l
Ensure that we don't print duplicate board names when -l is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
2014-11-26 20:25:40 -07:00
Simon Glass
0b5b409acc patman: Use the full commit hash for 'git checkout'
Even with the initial 8 characeters of the hash we will sometimes get a
collision. Use the full hash.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-26 20:25:39 -07:00
Tom Rini
ce267335c3 buildman: Save *.img files too
When saving binary files we likely want to keep any .img files that have
been generated as well.

Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-26 20:25:39 -07:00
Simon Glass
f80a8bbee8 sandbox: Fix warnings in cpu.c and os.c
This fixes the following two problems:

cppcheck reports:
[arch/sandbox/cpu/start.c:132]: (error) Uninitialized variable: err
[arch/sandbox/cpu/os.c:371]: (error) Memory leak: fname

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Denk <wd@denx.de>
2014-11-26 20:25:39 -07:00
Simon Glass
e48f3741c3 sandbox: Fix warnings due to 64-bit printf() strings
Now that we have inttypes.h, use it in a few more places to avoid compiler
warnings on sandbox when building on 64-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-26 20:25:39 -07:00
Sanchayan Maity
2260457341 mtd/nand/vf610_nfc: Disable subpage writes
This patch disables subpage writes for vf610_nfc nand
driver. This is required, as without this fix, writing
unaligned u-boot images with DFU results in a hang.
Trying to write unalgined binary images also results
in a hang, without disabling subpage writes.

Patch has been tested on a Colibri VF61 module.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2014-11-26 19:53:49 -06:00
Masahiro Yamada
f09eb52b3f mtd: denali: set some registers after nand_scan_ident()
Some but not all of implementations of the Denali NAND controller
have hardware circuits to detect the device parameters such as
page_size, erase_size, etc.  Even on those SoCs with such hardware
supported, the hardware is known to detect wrong parameters for some
nasty (almost buggy) NAND devices.  The device parameters detected
during nand_scan_ident() are more trustworthy.

This commit sets some hardware registers to mtd->pagesize,
mtd->oobsize, etc. in the code between nand_scan_ident() and
nand_scan_tail().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
2014-11-26 19:53:22 -06:00
Masahiro Yamada
65e4145a20 mtd: denali: use CONFIG_SYS_NAND_SELF_INIT
Some variants of the Denali NAND controller need some registers
set up based on the device information that has been detected during
nand_scan_ident().

CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between
nand_scan_ident() and nand_scan_tail().  It is also helpful to reduce
the difference between this driver and its Linux counterpart because
this driver was ported from Linux.  Moreover, doc/README.nand recommends
to use CONFIG_SYS_NAND_SELF_INIT.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
2014-11-26 19:53:19 -06:00
Rostislav Lisovy
35c204d8a9 nand: reinstate lazy bad block scanning
Commit ff94bc40af
("mtd, ubi, ubifs: resync with Linux-3.14")
accidentally reverted part of the commit
13f0fd94e3
("NAND: Scan bad blocks lazily.").

Reinstate the change as by commit
fb49454b1b
("nand: reinstate lazy bad block scanning")

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Acked-by: Heiko Schocher <hs@denx.de>
2014-11-26 19:51:51 -06:00
Tom Rini
85bafb6da4 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-11-26 11:23:26 -05:00
Tom Rini
21008ad638 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Conflicts:
	drivers/mmc/fsl_esdhc.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-26 11:22:29 -05:00
Guillaume GARDET
d3e488eaf4 spl: Fix SPL EXT support
Commit 9f12cd0e06 has broken SPL EXT support.
This patch update error code check to get SPL EXT support working again.

Tested on a Pandaboard (rev. A3).

Reviewed-by: Suriyan Ramasami <suriyan.r@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
2014-11-26 11:21:16 -05:00
Tom Rini
878cd63e02 Merge branch 'master' of http://git.denx.de/u-boot-samsung 2014-11-26 11:21:16 -05:00
Tom Rini
f2ffe7da7f Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2014-11-26 11:21:16 -05:00
Tom Rini
1fc4e6f486 Merge git://git.denx.de/u-boot-fdt 2014-11-26 11:21:14 -05:00
Bin Meng
908ec6e4d1 tools: Add ifdtool to .gitignore
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
22e131ca00 x86: chromebook_link: Enable the Chrome OS EC
Enable the Chrome OS EC so that it can be used from U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
a6fa83f0e7 x86: chromebook_link: Enable the x86 emulator
Enable this so that it can be used instead of native execution if desired.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
8c6ec412b4 bios_emulator: Always print errors when opcode decode fails
This is a rare event and should not happen. When it does it is confusing to
work out why. At least we should print a message.

Adjust the emulator to always print decode errors to the console.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
b3521f2e49 bios_emulator: Add an option to enable debugging
At present there are DEBUG options spread around the place. If you enable
one and not another you can end up with an emulator that does not work,
since each file can have a different view of what the registers look like.
To fix this, create a global CONFIG_X86EMU_DEBUG option that keeps
everything consistent.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
a3c700ec76 bios_emulator: Allow a custom interrupt handler to be installed
Sometime we want to provide an interrupt handler for the ROM, Add a
function to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
4c59f95327 bios_emulator: Add vesa support and allow ROMs to be passed in as data
As well as locating the ROM on the PCI bus, allow the ROM to be supplied to
the emulator. Split the init up a little so that callers can supply their
own interrupt routines. Also allow a vesa mode to be provided, to be
selected once the BIOS run is complete.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
ad6edca379 bios_emulator: Allow x86 to use the emulator
There is an implicit assumption that x86 machines want to use raw I/O in the
BIOS emulator, but this should be selectable. Add an CONFIG_X86EMU_RAW_IO
option to control it instead.

Also fix a few bugs which cause warnings on x86 and adjust the Makefile to
remove the assumption that only PowerPC uses the emulator.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
62d0c5e153 x86: config: Enable video support for chromebook_link
Now that we have the required drivers, enable video support with a suitable
option ROM.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
f3e56fe369 x86: dts: Add video information to the device tree
This provides panel timing information needed by the video driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
effcf067df x86: Add initial video device init for Intel GMA
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range
of video devices. Add code to set up the hardware on ivybridge. Part of the
init happens in native code, part of it happens in a 16-bit option ROM for
those nostalgic for the 1970s.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
d040ac0a89 x86: Allow an option ROM to be built into U-Boot
Some x86 machines require a binary blob containing 16-bit initialisation
code for their video hardware. Allow this to be built into the x86 ROM so
that it is accessible during boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
998110241b x86: video: Add video driver for bare x86 boards
Add a very simple driver which uses vesa to discover the video mode and
then provides a frame buffer for use by U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2014-11-25 07:11:16 -07:00
Simon Glass
6854f87cbc pci: Add general support for execution of video ROMs
Some platforms don't have native code for dealing with their video
hardware. In some cases they use a binary blob to set it up and perform
required actions like setting the video mode. This approach is a hangover
from the old PC days where a ROM was provided and executed during startup.

Even now, these ROMs are supplied as a way to set up video. It avoids the
code for every video chip needing to be provided in the boot loader. But
it makes the video much less flexible - e.g. it is not possible to do
anything else while the video init is happening (including waiting hundreds
of milliseconds for display panels to start up).

In any case, to deal with this sad state of affairs, provide an API for
execution of x86 video ROMs, either natively or through emulation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:14 -07:00
Simon Glass
0ca2426bea x86: Add support for running option ROMs natively
On x86 machines we can use an emulator to run option ROMS as with other
architectures. But with some additional effort (mostly due to the 16-bit
nature of option ROMs) we can run them natively. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:38:57 -07:00
Simon Glass
647f56e74e Add support for Vesa BIOS extensions
For option ROMs we can use these extensions to request a particular video
mode. Add a header file which defines the binary interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:15 -07:00
Simon Glass
22465fc46c x86: Add vesa mode configuration options
Add Kconfig options to allow selection of a vesa mode on x86 machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:15 -07:00
Simon Glass
e34aef1de3 x86: Add GDT descriptors for option ROMs
Option ROMs require a few additional descriptors. Add these, and remove the
enum since we now have to access several descriptors from assembler.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
176bf4ce0c Introduce a header file for the BIOS emulator
We should have a public header so that users can avoid defining functions
themselves.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
ed0a2fbf14 x86: Add a definition of asmlinkage
This is needed to permit calling C from assembler without too much pain.
Add a definition for x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
1ccd452b07 x86: config: Enable SPI for chromebook_link
Enable SPI so that the SPI flash can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
24774278c9 x86: ivybridge: Add northbridge init functions
Add init for the northbridge, another part of the platform controller hub.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
d1ef1132bb x86: Drop some msr functions that we don't support
These are not available in U-Boot as yet, so drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
bb80be3916 x86: Add init for model 206AX CPU
Add the setup code for the CPU so that it can be used at full speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
0c9075e9ad x86: Add LAPIC setup code
Add code to set up the Local Advanced Peripheral Interrupt Controller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:11 -07:00
Simon Glass
b636dd1079 x86: Drop old CONFIG_INTEL_CORE_ARCH code
This is no-longer used, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:34:03 -07:00
Bin Meng
d51457583f x86: Remove unnecessary call to initr_enable_interrupts()
Actually initr_enable_interrupts() was never called in an x86 build
due to it was wrapped by CONFIG_x86 (typo of X86).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Bin Meng
1dae2e0eb6 x86: Refactor interrupt_init()
Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to
i8259_init() and create a new interrupt_init() in
arch/x86/cpu/interrupt.c to call i8259_init() followed by a
call to cpu_init_interrupts().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Bin Meng
a549f7497b x86: Remove cpu_init_r() for x86
Since cpu_init_interrupts() was moved out of cpu_init_r(), it is
useless to keep cpu_init_r() for x86, thus remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Bin Meng
4372a9eca5 x86: Call cpu_init_interrupts() from interrupt_init()
Currently cpu_init_interrupts() is called from cpu_init_r() to
setup the interrupt and exception of the cpu core, but at that
time the i8259 has not been initialized to mask all the irqs
and remap the master i8259 interrupt vector base, so the whole
system is at risk of being interrupted, and if interrupted,
wrong interrupt/exception message is shown.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
18739e2ccc x86: Add Intel speedstep and turbo mode code
Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
a6d4c45306 x86: ivybridge: Set up XHCI USB
Add init for XHCI so that high-speed USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
79b303467a x86: config: Enable USB on link
Enable USB support on link - there are two EHCI ports available.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
9baeca4b89 x86: ivybridge: Set up EHCI USB
Add init for EHCI so that USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
4896f4acc8 x86: dts: Add SATA settings for link
Add the requires settings to enable SATA on link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00