Commit graph

39782 commits

Author SHA1 Message Date
Alison Wang
0f5e5579f2 ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as default
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
York Sun
dda3b610ee arm/ls1021a: Add workaround for DDR erratum A008378
Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:13 -06:00
Sjoerd Simons
053b86e6d8 pci: tegra: Fix port information parsing
commit a62e84d7b1 incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root port, the
"reg" property should be parsed from the dtb (as was previously the
case).

With this patch i can successfully network boot my jetson tk1

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2015-01-23 17:25:30 -07:00
Bin Meng
fea1c47f54 x86: Fix various code format issues in start16.S
Various minor code format issues are fixed in start16.S:
- U-boot -> U-Boot
- 32bit -> 32-bit
- Use TAB instead of SPACE to indent
- Move the indention location of the GDT comment block

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
3b621ccabd x86: Test mtrr support flag before accessing mtrr msr
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
4949166906 x86: Save mtrr support flag in global data
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
566d1754d3 x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.c
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00
Simon Glass
d1a5d3c133 x86: config: Always scroll the display by 5 lines, for speed
Scrolling a line at a time is very slow for reasons that I don't understand.
It seems to take about 100ms to copy 4MB of RAM in the frame buffer. To cope
with this, scroll 5 lines each time.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00
Simon Glass
3c0b668f66 x86: video: Add support for CONFIG_CONSOLE_SCROLL_LINES
Some machines are very slow to scroll their displays. To cope with this,
support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows
the display to operate at an acceptable speed by scrolling 5 lines at
a time.

This same option is available for LCDs so when these systems are unified
this code can be unified also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-23 17:24:54 -07:00
Simon Glass
4a2708a097 x86: Access the VGA ROM when needed
Add code to the generic pci_rom file to access the VGA ROM in PCI space
when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00
Sebastien Ronsse
07570e7097 x86: Fix out of bounds irq handlers access
Using coreboot-x86_defconfig, the following error occurred prior to this modification:
CC	arch/x86/lib/interrupts
arch/x86/lib/interrupts.c: In function ‘do_irqinfo’:
arch/x86/lib/interrupts.c:134:24: error: iteration 16u invokes undefined behavior [-Werror=aggressive-loop-optimizations]
   if (irq_handlers[irq].handler != NULL) {
                        ^
arch/x86/lib/interrupts.c:133:2: note: containing loop
  for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) {
  ^
cc1: all warnings being treated as errors
scripts/Makefile.build:275: recipe for target 'arch/x86/lib/interrupts.o' failed
make[1]: *** [arch/x86/lib/interrupts.o] Error 1
Makefile:1093: recipe for target 'arch/x86/lib' failed
make: *** [arch/x86/lib] Error 2

Change-Id: I3572a822081b72ab760f1eb99442e1161d3d167e
Signed-off-by: Sebastien Ronsse <sronsse@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00
Bin Meng
4df2b48fbe x86: ahci: Make sure interface is not busy after enabling the port
Each time U-Boot boots on Intel Crown Bay board, the displayed hard
drive information is wrong. It could be either wrong capacity or just
a 'Capacity: not available' message. After enabling the debug switch,
we can see the scsi inquiry command did not execute successfully.
However, doing a 'scsi scan' in the U-Boot shell does not expose
this issue.

SCSI:  Target spinup took 0 ms.
SATA link 1 timeout.
AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
ahci_device_data_io: 0 byte transferred.   <--- scsi inquiry fails
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
  Device 0: (0:0) Vendor: ATA Prod.:  Rev: ?8
              Type: Hard Disk
	                  Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512)
			  Found 1 device(s).

So uninitialized contents on the stack were passed to dev_print() to
display those wrong information.

The symptom were observed on two hard drives (one is Seagate, the
other one is Western Digital). The fix is to make sure the AHCI
interface is not busy by checking the error and status information
from task file register after enabling the port in ahci_port_start()
before proceeding other operations like scsi_scan().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:53 -07:00
Simon Glass
edb8b7a66b x86: Drop the x86_fb driver
Now that we have a full VESA driver we may as well use that. We need to
support the VESA layer being set up by early start-up code or by
running a VGA ROM.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:53 -07:00
Simon Glass
6b1ba98450 x86: Add a VESA video driver
Add a driver intended to cope with any VESA-compatible x86 graphics
adapter. It will not support ROMs which use OpenFirmware (Forth) since
there is no support for that in U-Boot. This means that MAC OS cards
will not work.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:16 -07:00
Simon Glass
c5caba0366 x86: pci: Don't stop when we get a vendor/device mismatch
These are quite common and we may as well press on and not be so picky.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-23 17:24:16 -07:00
Simon Glass
222f25f855 bios_emulator: Add some VESA interface debugging
Allow the supported modes to be listed when in debug mode.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:16 -07:00
Simon Glass
e78dd86998 bios_emulator: Don't display error when emulator terminates
As it turns out this is a normal condition, so suppress the error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:15 -07:00
Simon Glass
bdc88d4eb3 x86: Support ROMs on other archs
We shouldn't assume that the VGA ROM can always be loaded at c0000. This
is only true on x86 machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-23 17:24:15 -07:00
Simon Glass
40305240c6 x86: Correct endianness isues in pci_rom
This code is too x86-dependent at present. Correct it so that it can run on
big-endian machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-23 17:24:15 -07:00
Simon Glass
e5bc97578c bios_emulator: Fix an #ifdef typo in the header file
This stops the debug mode from working properly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-23 17:24:15 -07:00
Masahiro Yamada
37b608a52d powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
2015-01-23 16:56:09 -05:00
Masahiro Yamada
a258e732a7 powerpc: mpc5xxx: PM520 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Josef Wagner <Wagner@Microsys.de>
2015-01-23 16:55:57 -05:00
Masahiro Yamada
ad734f7dc2 powerpc: mpc5xxx: remove Total5200 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 16:53:52 -05:00
Masahiro Yamada
5344cc1a82 powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards
These boards are still non-generic boards.

It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
2015-01-23 16:53:36 -05:00
Masahiro Yamada
168dcc6cef powerpc: mpc85xx: remove P2020DS board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 16:53:17 -05:00
Masahiro Yamada
891235366d powerpc: mpc85xx: remove P2020COME board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Ira W. Snyder <iws@ovro.caltech.edu>
2015-01-23 16:53:12 -05:00
Masahiro Yamada
743d48151d powerpc: mpc85xx: remove P1_P2_RDB boards
These boards are still non-generic boards:
P1011RDB, P1022RDB, P2010RDB, P2020RDB

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2015-01-23 16:53:06 -05:00
Masahiro Yamada
8d1e3cb140 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Dave Liu <daveliu@freescale.com>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
2015-01-23 16:53:00 -05:00
Tom Rini
3b95288a2a Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-01-23 10:22:29 -05:00
Ian Campbell
4e7c892d15 sunxi: Use a common CONFIG_SYS_PROMPT
The CPU info is already logged during boot e.g.
   CPU:    Allwinner A20 (SUN7I)
so the prompt is just one more thing to change for each new SoC, just makes it
"sunxi#" instead.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-23 15:15:51 +01:00
Hans de Goede
faffd4a5cb sunxi: Add Hyundai A7HD support
The Hyundai A7HD is a 7" 16:9 A10 powered tablet featuring 1G RAM, 8G
nand, 1024x600 IPS screen, a mini hdmi port, mini usb receptacle and a
headphones port for details see: http://linux-sunxi.org/Hyundai_A7HD

Cc: Mark Janssen <maniac@maniac.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-23 15:15:11 +01:00
Hans de Goede
a7403ae84d sunxi: video: Make pwm polarity configurable
It turns out that there are some panels where the pwm input is not active low,
so make it configurable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-23 15:15:02 +01:00
Ian Campbell
c17fb11c56 sunxi: Add support for Mele M5.
HDMI, SATA, USB and Ethernet appear functional, I've not done extensive tests
of all peripherals though.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-23 15:15:02 +01:00
Hans de Goede
389046be2f sunxi: Convert sun7i boards to use auto dram configuration
Currently we've separate detailed dram settings for all sun7i boards, this
moves them over to using auto dram configuration so that we can get rid of
all the per board dram_foo.c files.

This has been tested on a A20-Olinuxino-Lime, A20-Olinuxino_MICRO, Bananapi,
Bananapro, Cubieboard2, Cubietruck, Mele_M3 and a Linksprite_pcDuino3.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-23 15:15:02 +01:00
Hans de Goede
56333be9b2 sunxi: Drop qt840a_defconfig
The qt840a is one of the many tv-boxes using the "i12" A20 pcb, but it
populates only one of the 2 places for a 16 bit dram ic, thus reducing
the buswidth to 16 bits, and the amount of ram to 512M, which is why we
had a separate config for it.

This commit switches the generic i12-tvbox_defconfig over to DRAM
autoconfiguration, so that it will work with the qt840a too, and drops the
qt840a specific config, like we've done with other memory-amount specific
configs before.

Tested on a generic i12-tvbox with 32 bit bus-width / 1G RAM, and on a
qt840a with 16 bit bus-width / 512M RAM.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-23 15:15:02 +01:00
Hans de Goede
89c95b0811 sunxi: Add new Chuwi V7 CW0825 board / defconfig
The Chuwi V7 is an A10 (sun4i) based tablet with 1G of RAM, 16G of nand flash,
microsd slot, 7" 1024x768 lvds ips panel, mini hdmi out, headphones out,
stereo speakers, front & back camera and usb wifi.

It is clearly marked "CHUWI", "V7" and "Model: CW0825" on the back of the
tablet.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-23 15:15:02 +01:00
Hans de Goede
27515b20c1 sunxi: video: Add support for Hitachi tx18d42vm LVDS LCD panels
Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
lcd controller which needs to be initialized over SPI, once that is
done they work like a regular LVDS panel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-23 15:14:53 +01:00
Tom Rini
ec0cc98f2c Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-01-22 20:04:17 -05:00
Tom Rini
032c6867a2 Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2015-01-22 20:04:06 -05:00
Tom Rini
1d6a95011f Merge branch 'master' of git://git.denx.de/u-boot-mips 2015-01-22 20:04:05 -05:00
Hans de Goede
a5464f2bd2 video: Add support for Hitachi tx18d42vm LVDS LCD panels
Add support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
lcd controller which needs to be initialized over SPI, once that is
done they work like a regular LVDS panel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-22 20:44:33 +01:00
Masahiro Yamada
0ba924a4ec ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2
PH1-sLD3, PH1-LD6b have DDR channel 2.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:52:16 +09:00
Masahiro Yamada
367a0d51db ARM: UniPhier: rename SG_MEMCONF_* macros for readability
Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined
by <linux/sizes.h> for readability.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:52:14 +09:00
Masahiro Yamada
4a35d60718 ARM: UniPhier: use <linux/sizes.h> for readability
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:52:06 +09:00
Masahiro Yamada
ee94ee3464 ARM: UniPhier: remove non-sense inline directives
The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:51:44 +09:00
Masahiro Yamada
ec79c79824 ARM: UniPhier: add static to local functions
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:51:21 +09:00
Masahiro Yamada
448437496b ARM: UniPhier: fix IECTRL set code for PH1-Pro4
For PH1-Pro4, the bit 6 of the IECTRL must be set.  It is the only
available bit in this register.  There is no effect of the write
access to the other bits.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:50:57 +09:00
Masahiro Yamada
061ae4c0bb ARM: UniPhier: describe init_page_table shorter
The assembly directive ".rept ... .endr" allows us to write the
init_page_table much shorter.  To make things further simpler,
set the text and stack area as Normal Memory, and the other sections
as Device attribute.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:50:21 +09:00
Masahiro Yamada
89a7c773ea ARM: UniPhier: fix comments in SoC Glue init function
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 00:49:57 +09:00
Masahiro Yamada
d6bc30af52 ARM: UniPhier: remove __packed that causes a problem on GCC 4.9
The DDR PHY training function, ddrphy_prepare_training() would not
work if compiled with GCC 4.9.

The struct ddrphy (arch/arm/include/asm/arch-uniphier/ddrphy-regs.h)
is specified with __packed because it represents a hardware register
mapping, but it turned out to cause a problem on GCC 4.9.

If -mno-unaligned-access is specified (yes, it is in
arch/arm/cpu/armv7/config.mk), GCC 4.9 is aware of the
__attribute__((packed)) and generates extra instructions to perform
the memory access in a way that does not cause unaligned access.
(Actually it is not need here because the register base, the first
argument of the ddrphy_prepare_training(), is always given with a
4-byte aligned address.)

Anyway, as a result, readl() / writel() is divided into byte-wise
accesses.  The problem is that this hardware only accepts 4-byte
register access.  Byte-wise accesses lead to unexpected behavior.

There are some options to avoid this problem.

[1] Remove -mno-unaligned-access
[2] Add __aligned(4) along with __packed to struct ddrphy
[3] Remove __packed from struct ddrphy

[1] solves the problem for ARMv7, but it does not for pre-ARMv6 and
ARMv6-M architectures where -mno-unaligned-access is default.
So, [1] does not seem reasonable in terms of code portability.

Both [2] and [3] work well, but [2] seems too much.  All the members
of struct ddrphy have the u32 type.  No padding would be inserted
even if __packed is dropped.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
2015-01-23 00:44:17 +09:00