Commit graph

13 commits

Author SHA1 Message Date
Michal Simek
eb8c54bfaa ARM: zynq: ehci: Added USB host driver support
Added USB host driver for zynq.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:35 +02:00
Michal Simek
3cc3fa8672 ARM: zynq: Add MIO detection code
Add run-time MIO pin detection to get actual
pin configuration for specific periphery.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:35 +02:00
Michal Simek
2da7a745b6 ARM: zynq: Setup correct slcr_lock value
The driver should setup slcr state according
to slcr operations.

Reported-by: Andrey Filippov <andrey@elphel.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:34 +02:00
Michal Simek
6e04769caf ARM: zynq: slcr: Fix incorrect commentary
Fix c&p error in zynq_slcr_devcfg_enable() commentary
and extending it with description according
to Zynq TRM also in zynq_slcr_devcfg_disable().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:34 +02:00
Michal Simek
3b5b599f17 ARM: zynq: Fix sparse warnings in slcr.c
Warnings:
arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static?
arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static?

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:33 +02:00
Soren Brinkmann
97598fcf10 net: zynq_gem: Calculate clock dividers dynamically
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19 09:41:21 +01:00
Soren Brinkmann
1cd46ed2d3 net: zynq_gem: Move RCLK details out of driver
The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19 09:41:21 +01:00
Jagannadha Sutradharudu Teki
b3de92495f zynq: Add support to find bootmode
Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.

Added this functionality on board_late_init as it's not
needed for normal initializtion part.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-10 15:18:33 +01:00
Michal Simek
39523bef29 zynq: slcr: Wait 100ms till clk is properly setup
If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-08-12 08:59:55 +02:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Michal Simek
d5dae85f23 fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.

The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:24 +02:00
Michal Simek
80243528ef net: gem: Fix gem driver on 1Gbps LAN
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:19 +02:00
Michal Simek
59c651f4e2 arm: zynq: Add SLCR support with system reset
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-07 09:18:42 +01:00