Commit graph

17 commits

Author SHA1 Message Date
Becky Bruce
9cd32426f2 86xx: Remove old-style law setup code
This includes mpc8610hpcd, mpc8641hpcn, and sbc8641d.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-01-24 12:12:40 -06:00
Becky Bruce
4933b91f8a 86xx: Support new law setup method and convert mpc8641
Adds the support code in cpu/mpc86xx for the new law setup code
recently created fsl_law.c, and changes the MPC8641HPCN config
to use this code.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-01-24 12:12:30 -06:00
Becky Bruce
b830b7f163 86xx: Support 2GB DIMMs
Configure the number of bits used to address the banks inside the SDRAM
device.  The default register value of 0 means 2 bits to address 4 banks.
Higher capacity devices like a 2GB DIMM require 3 bits to address 8 banks.

Signed-off-by: Becky Bruce <bgill@freescale.com>
2008-01-10 14:00:28 -06:00
Wolfgang Denk
409ecdc0bb Fix compiler warnings for PPC systems. Update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-11-18 16:36:27 +01:00
Jon Loeliger
d08b7233bc 86xx: Fix broken variable reference when #def DEBUGing.
Sometimes you can't reference the DDR2 controller variables.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-11-17 00:58:10 +01:00
Jon Loeliger
2491167c24 86xx: Allow for fewer DDR slots per memory controller.
As a direct correlation exists between DDR DIMM slots
and SPD EEPROM addresses used to configure them, use
the individually defined SPD_EEPROM_ADDRESS* values to
determine if a DDR DIMM slot should have its SPD
configuration read or not.

Effectively, this now allows for 1 or 2 DIMM slots
per memory controller.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-10-16 16:36:36 +02:00
James Yang
c1ab82669d Rewrote picos_to_clk() to avoid rounding errors.
Clarified that conversion is to DRAM clocks rather than platform clocks.
Made function static to spd_sdram.c.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-05-01 11:36:59 -05:00
Ed Swarthout
2ccceacc04 Add support for 8641 Rev 2 silicon.
Without this patch, I am unable to get to the prompt on rev 2 silicon.
Only set ddrioovcr for rev1.

Signed-off-by: Ed Swarthout<ed.swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-03-22 11:02:34 -05:00
Jon Loeliger
ea08ff6e14 MPC86xx: Cleaned up unused and conditionally used local variables.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-10-27 17:46:10 +02:00
Jon Loeliger
1fd5699a4a Coding style changes to remove local varible blocks
and reformat a bit nicer.
2006-10-10 17:19:03 -05:00
John Traill
f55df18187 Fix missing tCycle/modfreq calculation.
Signed-off-by: John Traill <john.traill@freescale.com>
2006-09-29 09:13:39 -05:00
Jon Loeliger
cd6d73d5b8 Remove bogus msync and use volatile asm. 2006-08-29 09:48:49 -05:00
John Traill
91a414c7d1 Fix caslat calculation
Signed-off-by: John Traill <john.traill@freescale.com>
2006-08-09 11:06:25 -05:00
Haiying Wang
70205e5a6d Fix two SDRAM setup bugs.
Fix ECC setup bug.
    Enable 1T/2T based on number of DIMMs present.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2006-05-30 08:51:19 -05:00
Jon Loeliger
9a655876e5 Enable dual DDR controllers and interleaving. 2006-05-19 13:54:02 -05:00
Jon Loeliger
5c9efb36a6 Cleanup whitespaces and style issues.
Removed //-style comments.
Use 80-column lines.
Remove trailing whitespace.
Remove dead code and debug cruft.
2006-04-27 10:15:16 -05:00
Jon Loeliger
debb7354d1 Initial support for MPC8641 HPCN board. 2006-04-26 17:58:56 -05:00