mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
86xx: Support new law setup method and convert mpc8641
Adds the support code in cpu/mpc86xx for the new law setup code recently created fsl_law.c, and changes the MPC8641HPCN config to use this code. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
This commit is contained in:
Becky Bruce
Jon Loeliger
parent
1a41f7ce9c
commit
4933b91f8a
6 changed files with 90 additions and 2 deletions
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o
|
||||
COBJS := $(BOARD).o law.o
|
||||
|
||||
SOBJS := init.o
|
||||
|
||||
|
|
|
|||
64
board/freescale/mpc8641hpcn/law.c
Normal file
64
board/freescale/mpc8641hpcn/law.c
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration:
|
||||
*
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G
|
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
|
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
|
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M
|
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
|
||||
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
|
||||
* 0xf800_0000 0xf80f_ffff CCSRBAR 1M
|
||||
* 0xf810_0000 0xf81f_ffff PIXIS 1M
|
||||
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
|
||||
*
|
||||
* Notes:
|
||||
* CCSRBAR don't need a configured Local Access Window.
|
||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
||||
*/
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
|
||||
#endif
|
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
|
||||
SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
|
||||
SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
|
||||
SET_LAW_ENTRY(5, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
|
||||
SET_LAW_ENTRY(6, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
|
||||
SET_LAW_ENTRY(7, (CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
|
||||
#endif
|
||||
SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
|
|
@ -49,6 +49,10 @@ void cpu_init_f(void)
|
|||
/* Clear initial global data */
|
||||
memset ((void *) gd, 0, sizeof (gd_t));
|
||||
|
||||
#ifdef CONFIG_FSL_LAW
|
||||
init_laws();
|
||||
#endif
|
||||
|
||||
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
|
||||
* addresses - these have to be modified later when FLASH size
|
||||
* has been determined
|
||||
|
|
@ -114,5 +118,8 @@ void cpu_init_f(void)
|
|||
*/
|
||||
int cpu_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_LAW
|
||||
disable_law(0);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
#include <i2c.h>
|
||||
#include <spd.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
#include <asm/fsl_law.h>
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void dma_init(void);
|
||||
|
|
@ -1179,12 +1179,16 @@ spd_sdram(void)
|
|||
/*
|
||||
* Set up LAWBAR for DDR 1 space.
|
||||
*/
|
||||
#ifdef CONFIG_FSL_LAW
|
||||
set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
|
||||
#else
|
||||
mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
|
||||
mcm->lawar1 = (LAWAR_EN
|
||||
| LAWAR_TRGT_IF_DDR_INTERLEAVED
|
||||
| (LAWAR_SIZE & law_size_interleaved));
|
||||
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
|
||||
debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
|
||||
#endif
|
||||
debug("Interleaved memory size is 0x%08lx\n", memsize_total);
|
||||
|
||||
#ifdef CONFIG_DDR_INTERLEAVE
|
||||
|
|
@ -1239,12 +1243,16 @@ spd_sdram(void)
|
|||
/*
|
||||
* Set up LAWBAR for DDR 1 space.
|
||||
*/
|
||||
#ifdef CONFIG_FSL_LAW
|
||||
set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
|
||||
#else
|
||||
mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
|
||||
mcm->lawar1 = (LAWAR_EN
|
||||
| LAWAR_TRGT_IF_DDR1
|
||||
| (LAWAR_SIZE & law_size_ddr1));
|
||||
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
|
||||
debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
||||
|
|
@ -1269,6 +1277,11 @@ spd_sdram(void)
|
|||
/*
|
||||
* Set up LAWBAR for DDR 2 space.
|
||||
*/
|
||||
#ifdef CONFIG_FSL_LAW
|
||||
set_law(8,
|
||||
(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
|
||||
law_size_ddr2, LAW_TRGT_IF_DDR_2);
|
||||
#else
|
||||
if (ddr1_enabled)
|
||||
mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
|
||||
& 0xfffff);
|
||||
|
|
@ -1280,6 +1293,7 @@ spd_sdram(void)
|
|||
| (LAWAR_SIZE & law_size_ddr2));
|
||||
debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
|
||||
debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
|
||||
#endif
|
||||
}
|
||||
|
||||
debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
|
||||
|
|
|
|||
|
|
@ -283,8 +283,10 @@ in_flash:
|
|||
bl setup_ccsrbar
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_FSL_LAW
|
||||
bl law_entry
|
||||
sync
|
||||
#endif
|
||||
|
||||
/* run low-level CPU init code (from Flash) */
|
||||
bl cpu_init_f
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
|
||||
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
|
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
|
|
|||
Loading…
Reference in a new issue