Commit graph

138 commits

Author SHA1 Message Date
Simon Glass
b697e0ff5b dm: tpm: Convert I2C driver to driver model
Convert the tpm_tis_i2c driver to use driver model and update boards which
use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2015-08-31 07:57:28 -06:00
Masahiro Yamada
0f9258228e of: clean up OF_CONTROL ifdef conditionals
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL.  We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:

 #ifdef CONFIG_OF_CONTROL
 # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL)
 #  define OF_CONTROL 0
 # else
 #  define OF_CONTROL 1
 # endif
 #else
 # define OF_CONTROL 0
 #endif

Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute.  It refers to
CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for
SPL.

Also, we no longer have to cancel CONFIG_OF_CONTROL in
include/config_uncmd_spl.h and scripts/Makefile.spl.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-18 13:46:05 -04:00
Masahiro Yamada
dffb86e468 of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL
As we discussed a couple of times, negative CONFIG options make our
life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
and here is another one.

Now, there are three boards enabling OF_CONTROL on SPL:
 - socfpga_arria5_defconfig
 - socfpga_cyclone5_defconfig
 - socfpga_socrates_defconfig

This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
the logic.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-18 13:46:04 -04:00
Masahiro Yamada
cc7aebe819 fdtdec: fix OF_CONTROL switch
There is no case where defined(SPL_DISABLE_OF_CONTROL) is true.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-18 13:46:04 -04:00
Andrew Bradford
f3b84a3032 x86: baytrail: Configure FSP UPD from device tree
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-14 03:24:21 -06:00
Marek Vasut
6ab00db226 arm: socfpga: misc: Reset ethernet from OF
Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc
hardcoded values in the U-Boot code. Since we don't have a proper reset
framework in place yet, we have to do this slightly ad-hoc parsing of the
OF tree instead.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2015-08-08 14:14:08 +02:00
York Sun
28445aa7ec lib/fdtdec: Fix fdt_addr_t and fdt_size_t typedef
fdt_addr_t is a physical address. It can be either 64-bit or 32-bit,
depending on the architecture. It should be phys_addr_t instead of
u64 or u32. Similarly, fdt_size_t is changed to phys_size_t.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
2015-08-06 07:31:36 -06:00
Simon Glass
5ae3a5e887 dts: Drop unused compatible ID for the NXP video bridge
This has moved to driver model so we can drop the fdtdec support.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:17 -06:00
Simon Glass
68964dbc83 video: Remove the old parade driver
We have a new one which uses driver model and device tree configuration.
Remove the old one.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:16 -06:00
Simon Glass
05bccbcd76 power: Remove old TPS65090 drivers
Remove the old drivers (both the normal one and the cros_ec one) now that
we have new drivers that use driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:16 -06:00
Tom Warren
7aaa5a60ce ARM: Tegra210: Add support to common Tegra source/config files
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28 10:30:20 -07:00
Simon Glass
257bfd2e21 dm: usb: tegra: Drop legacy USB code
Drop the code that doesn't use driver model for USB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-10 19:26:55 -06:00
Simon Glass
af28224546 sandbox: Move CONFIG_SANDBOX_SERIAL to Kconfig
Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-10 19:26:55 -06:00
Gabriel Huau
5318f18d2c x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:32:08 -06:00
Bin Meng
9c7dea602e x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Simon Glass
00f3732752 tegra: video: Support serial output resource (SOR) on tegra124
The SOR is required for talking to eDP LCD panels. Add a driver for this
which will be used by the DisplayPort driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:11 -07:00
Simon Glass
12e671142d fdt: Add binding decode function for display-timings
This is useful for display parameters. Add a simple decode function to read
from this device tree node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:06 -07:00
Simon Glass
f56da290b8 dm: usb: exynos: Drop legacy USB code
Drop the code that doesn't use driver model for USB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-05-06 14:00:35 -06:00
Simon Glass
b2b0d3e712 dm: core: Select device tree control correctly for SPL
Some boards will not use device tree for SPL even with driver model. Add
the logic to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-23 09:05:54 -06:00
Simon Glass
0879361fd3 fdt: Rename setup_fdt() and make it prepare also
There is little reason to split these two functions. Bring them together
which simplifies the init sequence.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-23 09:05:53 -06:00
Simon Glass
b45122fdf5 fdt: sandbox: Move setup code from board_f to fdtdec
We want to be able to set up the device tree in SPL, so move this code
to a common place.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-23 09:05:53 -06:00
Simon Glass
3fbb78711c cros_ec: exynos: Match up device tree with kernel version
The U-Boot device trees are slightly different in a few places. Adjust them
to remove most of the differences. Note that U-Boot does not support the
concept of interrupts as distinct from GPIOs, so this difference remains.

For sandbox, use the same keyboard file as for ARM boards and drop the
host emulation bus which seems redundant.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
ce6adaa4b5 fdt: Drop LPC compatible string in fdtdec
This is not needed now that we have moved chromebook_link and cros_ec to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
672055e20b fdt: cros_ec: Drop compatible string in fdtdec
This is not needed now that we have moved to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
90b16d1491 x86: chromebook_link: dts: Add PCH and LPC devices
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.

Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
106cce9604 fdt: Tighten up error handling in fdtdec_get_pci_addr()
This function returns -ENOENT when the property is missing (which the caller
might forgive) and also when the property is present but incorrectly
formatted (which many callers would like to report).

Update the error return value to allow these different situations to be
distinguished.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-16 19:27:42 -06:00
Simon Glass
5f7bfdd630 fdt: Export fdtdec_get_number() for general use
This function is missing a prototype but is more widey useful. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-04-16 19:27:41 -06:00
Bin Meng
0eb9dc76e2 fdtdec: Improve fdtdec_get_pci_bdf() documentation
Add the description that how the compatible property is involved in
the fdtdec_get_pci_bdf() documentation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-03-24 21:22:37 -06:00
Masahiro Yamada
6462cdedc2 ARM: UniPhier: adjust device trees for business transfer
Panasonic's System LSI products, UniPhier SoC family, have been
transferred to Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-15 13:37:00 +09:00
Masahiro Yamada
1e7df7c4e4 usb: UniPhier: add UniPhier on-chip xHCI host driver support
Support xHCI host driver used on Panasonic UniPhier platform.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-03-01 00:03:00 +09:00
Bin Meng
c89ada017f fdtdec: Add compatible id and string for Intel Quark MRC
Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can
decode Intel Quark MRC node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:43 -07:00
Simon Glass
b9749eb5e4 dm: exynos: Drop unused COMPAT features for SPI
This has moved to driver model so we don't need the fdtdec support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2015-01-29 17:09:57 -07:00
Simon Glass
dedff1a000 dm: tegra: Drop unused COMPAT features for I2C, SPI
These have moved to driver model so we don't need the fdtdec support.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:56 -07:00
Simon Glass
009067c3b7 dm: fdt: Remove the old GPIO functions
Now that we support device tree GPIO bindings directly in the driver model
GPIO uclass we can remove these functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:53 -07:00
Simon Glass
57068a7aeb dm: fdt: Add a function to decode phandles with arguments
For GPIOs and other functions we want to look up a phandle and then decode
a list of arguments for that phandle. Each phandle can have a different
number of arguments, specified by a property in the target node. This is
the "#gpio-cells" property for GPIOs.

Add a function to provide this feature, taken modified from Linux 3.18.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:50 -07:00
Simon Glass
5da38086bd x86: dts: Add compatible string for Intel ICH9 SPI controller
Add this to the enum so that we can use the various fdtdec functions. A
later commit will move this driver to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 21:44:59 -07:00
Bin Meng
a62e84d7b1 fdt: Add several apis to decode pci device node
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
2015-01-13 07:24:40 -08:00
Thierry Reding
f315828b0d pci: tegra: Add Tegra PCIe driver
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.

This is based on the Linux kernel driver, originally submitted upstream
by Mike Rapoport.

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
79c7a90f6c ARM: tegra: Implement XUSB pad controller
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
6173c45b21 power: Add AMS AS3722 PMIC support
The AS3722 provides a number of DC/DC converters and LDOs as well as 8
GPIOs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Tom Rini
88342103cc Merge git://git.denx.de/u-boot-fdt 2014-12-01 15:24:26 -05:00
Tom Rini
f4e7e2d121 Merge git://git.denx.de/u-boot-x86 2014-12-01 15:24:07 -05:00
Masahiro Yamada
0bd4e39d2b fdt: remove fdtdec_get_alias_node() function
The fdt_path_offset() checks an alias too.

fdtdec_get_alias_node(blob, "foo") is equivalent to
fdt_path_offset(blob, "foo").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-27 09:12:30 -07:00
Tom Rini
1fc4e6f486 Merge git://git.denx.de/u-boot-fdt 2014-11-26 11:21:14 -05:00
Simon Glass
effcf067df x86: Add initial video device init for Intel GMA
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range
of video devices. Add code to set up the hardware on ivybridge. Part of the
init happens in native code, part of it happens in a 16-bit option ROM for
those nostalgic for the 1970s.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
bb80be3916 x86: Add init for model 206AX CPU
Add the setup code for the CPU so that it can be used at full speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
3ac839352d x86: ivybridge: Add SATA init
Add code to set up the SATA interfaces on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
65dd74a674 x86: ivybridge: Implement SDRAM init
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.

There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
77f9b1fb62 x86: ivybridge: Perform Intel microcode update on boot
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
a9f04d49e5 fdt: Add a function to decode a variable-sized u32 array
Sometimes an array can be of variable size up to a maximum. Add a helper
function to decode this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:11 +01:00