Commit graph

215 commits

Author SHA1 Message Date
Chris Packham
b755abecd4 net: mv88e61xx: Add support for fixed links
On some boards these switches are wired directly into a SERDES
interface on another Ethernet MAC. Add the ability to specify
these kinds of boards using CONFIG_MV88E61XX_FIXED_PORTS which defines
a bit mask of these fixed ports.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13 12:25:18 -05:00
Chris Packham
65d4d00abc net: Add support for mv88e609x switches
The Marvell Link Street mv88e60xx is a series of FastEthernet switch
chips, some of which also support Gigabit ports. It is similar to the
mv88e61xx series which support Gigabit on all ports.

The main difference is the number of ports. Which affects the
PORT_COUNT define and the size of the mask passed to
mv88e61xx_port_set_vlan().

Other than that it's just a matter of adding the appropriate chip
IDs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Cc: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13 12:25:14 -05:00
Mugunthan V N
ce412b79e7 drivers: net: phy: atheros: add separate config for AR8031
In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.

Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13 12:24:55 -05:00
Andrea Merello
2ec4d10b65 phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID
This adds support for internal delay on RX and TX on RGMII interface for the
AR8035 phy.

This is basically the same Linux driver do. Tested on a Zynq Zturn board (for
which u-boot support in is my tree; first patch waiting ML approval)

Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-13 12:24:51 -05:00
Masahiro Yamada
1221ce459d treewide: replace #include <asm/errno.h> with <linux/errno.h>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 17:55:42 -04:00
Joe Hershberger
dfcc496ed7 net: mii: Changes not made by spatch
If the functions passed to the registration function are not in the same
C file (extern) then spatch will not handle the dependent changes.

Make those changes manually.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

For the 4xx related files:
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-15 15:29:03 -05:00
Simon Glass
fbfa1aba91 net: phy: marvell: Add a missing errno.h header
This corrects a build error on zynqmp.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-27 14:15:54 -06:00
Mingkai Hu
19c9ddaa4f driver: net: phylib: add support for aquantia AQR106/107 PHY
This patch adds support for aquantia AQR106/107 PHY.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-07-06 10:45:04 -05:00
Nathan Rossi
08e64cece2 net: phy: marvell: Do not reset 88e1310 after autoneg
Commit a058052c "net: phy: do not read configuration register on reset",
changes the behaviour of the phy_reset function such that the state of
the BMCR register is not preserved during reset.

Change the config function for the m88e1310 so that it does not do a
reset after configuring auto-negotiation.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2016-06-21 17:01:52 -05:00
Alexey Firago
79887749f8 net: phy: micrel: add support for KSZ886x switches in MIIM mode
This patch adds a phy driver for the Micrel KSZ886x switches.

Similarly to the KSZ8895, SoC MAC is directly connected to the switch
MAC on the switch CPU port, so the link to the switch is always up.

KSZ886x switches can be used in the following configuration modes:
- Unmanaged mode with config stored in external EEPROM
- Managed mode over SPI
- Managed mode over I2C
- Managed mode over mdio/mdc (aka MIIM or SMI)

This patch supports only unmanaged and MIIM modes.

Based on Micrel KSZ886x driver from Linux kernel and
Micrel KSZ8895 driver from U-Boot.

Verified with the KSZ8863MLL.

Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-06-21 17:01:52 -05:00
Scott Wood
b616d9b0a7 nand: Embed mtd_info in struct nand_chip
nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.

This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip.  It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].

Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03 20:27:48 -05:00
Tom Rini
2ee490a024 Merge branch 'master' of git://git.denx.de/u-boot-net
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	drivers/net/zynq_gem.c
2016-05-24 11:59:02 -04:00
Dan Murphy
0a71cd7729 net: phy: dp83867: Add SGMII helper for configuration
The code assumed that if the interface is not RGMII configured
then it must be SGMII configured.  This device has the ability
to support most of the MII interfaces.  Therefore add the
helper for SGMII and only configure the device if the interface is
configured for SGMII.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:05 -05:00
Dan Murphy
3ab72fe807 net: phy: Move is_rgmii helper to phy.h
Move the phy_interface_is_rgmii to the phy.h
file for all phy's to be able to use the API.

This now aligns with the Linux kernel based on
commit e463d88c36d42211aa72ed76d32fb8bf37820ef1

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:05 -05:00
Dan Murphy
085445ca41 net: phy: ti: Allow the driver to be more configurable
Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree.  If the value is not set in the
devicetree then set the delay to the default.

If devicetree is not used then use the default defines within the
driver.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:42:04 -05:00
Kevin Smith
24ae3961f8 net: phy: Add PHY driver for mv88e61xx switches
The previous mv88e61xx driver was a driver for configuring the
switch, but did not integrate with the PHY/networking system, so
it could not be used as a PHY by U-boot.  This is a complete
rework to support this device as a PHY.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-05-24 11:39:04 -05:00
Kevin Smith
83c05515d8 net: Remove unused mv88e61xx switch driver
No boards are using this driver.  Remove in preparation for a new
driver with integrated PHY support.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
2016-05-24 11:39:04 -05:00
Michal Simek
1b008fdb06 phy: marvell: Do not reset phy after negotiation
The patch
"net: phy: do not read configuration register on reset"
(sha1: a058052c35)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 13:17:59 +02:00
Michal Simek
7a673f0b06 phy: Wire return value from phy_config()
Fix zynq_gem driver to handle error from phy_config correctly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 13:17:59 +02:00
Michal Simek
b733c278d7 net: phy: Handle phy_startup() error codes properly
Propagate error code from genphy_update_link() to phy startup().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-24 13:17:59 +02:00
Michal Simek
ef5e821bd8 phy: Return correct error code when timeout happens
Return -ETIMEDOUT if timeout happens.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-24 13:17:59 +02:00
Siva Durga Prasad Paladugu
85b949f40b net: phy: Add SGMII support for TI phy
Add support of SGMII to TI phy dp838367
Enable the SGMII and PCS settings in phy
control, CFG2 and BIST registers

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:28:39 +02:00
Siva Durga Prasad Paladugu
ed6fad3e25 phy: Add phy driver support for xilinx PCS/PMA core
Add phy driver support for xilinx PCS/PMA core

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-04 20:10:44 +02:00
Karsten Merker
563d8d9358 net: phy: Realtek RTL8211B/C PHY ID fix
The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a
wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.

The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F)
of the RTL8211 and the code originally applied a mask of 0xfffff0 to
the PHY ID, so that matching the PHY ID to the appropriate driver code
was only done on the chip type (RTL8211), but not on a specific
revision.

After introduction of support for the RTL8211E, which needed another
startup function than the older chip revisions, commit
4220504767 changed the mask to 0xffffff
to make the chip revision relevant for the match, but didn't provide
the now-relevant lower bits of the uid field for the RTL8211B/C.

Fix this by setting the full PHY ID in the RTL8211B_driver uid field.

Fixes: 4220504767 ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected")
Signed-off-by: Karsten Merker <merker@debian.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-04-02 19:26:08 -04:00
Michael Haas
525d187afb net: phy: Optionally force master mode for RTL PHY
This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this
define is set, RTL8211x PHYs (except for the RTL8211F) will have their
1000BASE-T master/slave autonegotiation disabled and forced to master
mode.

This is helpful for PHYs like the RTL8211C which produce unstable links
in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB
and A20-OLinuXino-Lime2.

There is no proper way to identify affected PHYs in software as the
RTL8211C shares its UID with the RTL8211B. Thus, this fix requires
the introduction of an #ifdef.

CC: fradav@gmail.com
CC: merker@debian.org
CC: hdegoede@redhat.com
CC: ijc@hellion.org.uk
CC: joe.hershberger@ni.com

Signed-off-by: Michael Haas <haas@computerlinguist.org>
Tested-by: Karsten Merker <merker@debian.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-03-31 14:29:11 +02:00
Alison Wang
903d384d40 net: phy: atheros: Fix problem with phy_reset() clearing BMCR
In commit <a058052c358c> [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION)
is cleared too. It causes auto-negotiation timeout error on Atheros's
PHY AR8033.

To fix this problem, genphy_config_aneg() and genphy_restart_aneg()
needs to be called in ar8035_config() to enable and restart
auto-negotiation.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-26 13:32:37 -06:00
Michal Simek
6a10bc5be8 net: phy: realtek: Use generic genphy_parse_link() for RTL8211E
The problem with current implementation is that SPDDONE bit is 1
but link bit is zero. That's why phydev->link is setup to 0
which ending up in driver failure that link is not up.

Log:
Zynq> dhcp
ethernet@e000b000 Waiting for PHY auto negotiation to complete.......
done
ethernet@e000b000: No link.

There is at least 1ms delay between spddone bit and link up.

Use genphy_read_status() instead of realtek implemenation which is
working with page 11. Linux driver is also using generic implementation.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-22 16:37:50 +01:00
Stefan Roese
a8c3eca433 net: phy: marvell: Fix problem with phy_reset() clearing BMCR
With commit a058052c [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Resulting in bit 12
being cleared (A/N enable). This leads to autonegotiation link problems,
at least on the Marvell Armada ClearFog board. I suspect that other
boards using this driver will be affected as well.

At the of m88e1111s_config(), phy_reset() is called. This is not needed
for the PHY to load the changed configuration, as phy_reset() is called
a few lines before already. So lets call genphy_restart_aneg() here
instead to start the AN correctly.

Tested on clearfog.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-18 11:32:03 -06:00
Stefan Roese
3089c47ddc net: phy: marvell: Call phy_reset() where possible
Instead of coding the soft PHY reset function multiple times in marvell.c,
lets call the common phy_reset() function from phy.c.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-18 11:32:00 -06:00
Mugunthan V N
347348f9f7 drivers: net: phy: micrel: fix build errors with CONFIG_DM_ETH
When Micrel phy is selected without CONFIG_PHY_MICREL_KSZ9031 or
CONFIG_PHY_MICREL_KSZ9021 there  is a build error. Fixing this
by adding proper ifdefs

drivers/net/phy/micrel.c:370:39: error: array type has incomplete element type
 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
                                       ^
drivers/net/phy/micrel.c:372:39: error: array type has incomplete element type
 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
                                       ^
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:377:23: error: array type has incomplete element type
  struct ksz90x1_ofcfg ofcfg[] = {
                       ^
drivers/net/phy/micrel.c:379:13: error: ‘ksz90x1_rxd_grp’ undeclared (first use in this function)
   { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
             ^
drivers/net/phy/micrel.c:379:13: note: each undeclared identifier is reported only once for each function it appears in
drivers/net/phy/micrel.c:380:13: error: ‘ksz90x1_txd_grp’ undeclared (first use in this function)
   { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
             ^
drivers/net/phy/micrel.c:386:3: warning: implicit declaration of function ‘ksz90x1_of_config_group’ [-Wimplicit-function-declaration]
   ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
   ^
drivers/net/phy/micrel.c:377:23: warning: unused variable ‘ofcfg’ [-Wunused-variable]
  struct ksz90x1_ofcfg ofcfg[] = {
                       ^
drivers/net/phy/micrel.c: At top level:
drivers/net/phy/micrel.c:370:39: warning: ‘ksz9031_ctl_grp’ defined but not used [-Wunused-variable]
 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
                                       ^
drivers/net/phy/micrel.c:372:39: warning: ‘ksz9031_clk_grp’ defined but not used [-Wunused-variable]
 static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
                                       ^
scripts/Makefile.build:277: recipe for target 'drivers/net/phy/micrel.o' failed
make[1]: *** [drivers/net/phy/micrel.o] Error 1
Makefile:1201: recipe for target 'drivers/net/phy' failed
make: *** [drivers/net/phy] Error 2
make: *** Waiting for unfinished jobs....

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-08 10:10:45 -05:00
Purna Chandra Mandal
46c9d938ca drivers: net: phy: add SMSC LAN8740 Phy support.
Add SMSC LAN8740 Phy support required for PIC32MZDA devices.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-01 22:14:02 +01:00
Tom Rini
82d72a1b99 Merge branch 'master' of git://git.denx.de/u-boot-net 2016-01-28 18:42:10 -05:00
Shaohui Xie
d8877e6f8c net: phy: implements probe for Cortina phy
Cortina phy cannot support soft reset, this commit implements probe
for Cortina PHY to tell phylib to skip phy soft reset by setting
PHY_FLAG_BROKEN_RESET in flags.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:31 -06:00
Shaohui Xie
ddcd1f3084 net: phy: introduce a quirk PHY_FLAG_BROKEN_RESET
Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip
soft reset. This commit uses 'flags' of phy device structure to store the
quirk.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:30 -06:00
Dinh Nguyen
ff7bd212cb net: phy: micrel: fix divisor value for KSZ9031 phy skew
The picoseconds to register value divisor(ps_to_regval) should be 60 and not
200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
divisor because the 4-bit skew values are defined from 0x0000(-420ps) to
0xffff(480ps), increments of 60.

For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7.
With the previous divisor of 200, it would result in 0x2, which represents a
-300ps delay.

With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with
1Gb ethernet.

References:
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:30 -06:00
Alexandre Messier
1f9e672c79 net: phy: Use 'autoneg' flag from phydev
Use the 'autoneg' flag available in phydev when checking if
autoneg is in use.

The previous implementation was checking directly in the PHY
if autoneg was supported. Some PHYs will report that autoneg
is supported, even when it is disabled. Thus it is not possible
to use that bit to determine if autoneg is currently in use or
not.

Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:29 -06:00
Alexandre Messier
53b0c38c7a net: phy: Set ANRESTART in setup_forced
When configuring a PHY in fixed (forced) link mode, in order for
the changes to be applied, either one of these conditions must
be triggered:
	1- PHY is reset
	2- Autoneg is restarted
	3- PHY transitions from power-down to power-up

Neither of these is currently done, so effectively the fixed link
configuration is not applied in the PHY.

Fix this by setting the Autoneg restart bit.

Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:28 -06:00
Alexandre Messier
79e3efd5e5 net: phy: micrel: Disable B_CAST on config
Micrel PHYs KSZ8021/31 and KSZ8081 have a feature where MDIO address 0
is considered as a broadcast address; the PHY will respond even if it
is not its configured (pinstrapped) address. This feature is enabled
by default.

The Linux kernel disables that feature at initialisation, but not
before it probes the MDIO bus. This causes an issue, because a PHY
at address 3 will be discovered at addresses 0 and 3, but will then
only respond at address 3. Because Linux attaches the first PHY it
discovers on 'eth0', it will attach the PHY from address 0, which
will never answer again.

Fix the issue by disabling the broadcast feature in U-Boot, before
Linux is started.

Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:21 -06:00
Alexey Brodkin
b18acb0a11 drivers/net/phy: introduce phy_set_supported()
This new function will allow MAC drivers to override supported
capabilities of the phy. It is required when MAC cannot handle all
speeds supported by phy.

For example phy supports up-to 1Gb connections while MAC may only work
in modes up to 100 or even 10 Mbit/sec.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:32:42 -06:00
Sascha Hauer
44bc317487 net: phy: genphy: Allow overwriting features
of_set_phy_supported allows overwiting hardware capabilities of
a phy with values from the devicetree. This does not work with
the genphy driver though because the genphys config_init function
will overwrite all values adjusted by of_set_phy_supported. Fix
this by initialising the genphy features in the phy_driver struct
and in config_init just limit the features to the ones the hardware
can actually support. The resulting features are a subset of the
devicetree specified features and the hardware features.

This is a copy of the patch from Linux kernel, see
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c242a47238fa2a6a54af8a16e62b54e6e031d4bc

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:32:41 -06:00
Florian Fainelli
bbdcaff12a net: phy: ensure Gigabit features are masked off if requested
When a Gigabit PHY device is connected to a 10/100Mbits capable Ethernet
MAC, the driver will restrict the phydev->supported modes to mask off
Gigabit. If the Gigabit PHY comes out of reset with the Gigabit features
set by default in MII_CTRL1000, it will keep advertising these feature,
so by the time we call genphy_config_advert(), the condition on
phydev->supported having the Gigabit features on is false, and we do not
update MII_CTRL1000 with updated values, and we keep advertising Gigabit
features, eventually configuring the PHY for Gigabit whilst the Ethernet
MAC does not support that.

This patches fixes the problem by ensuring that the Gigabit feature bits
are always cleared in MII_CTRL1000, if the PHY happens to be a Gigabit
PHY, and then, if Gigabit features are supported, setting those and
updating MII_CTRL1000 accordingly.

This is a copy of patch from Linux kernel, see
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=5273e3a5ca94fbeb8e07d31203069220d5e682aa

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:31:30 -06:00
Stefan Agner
a058052c35 net: phy: do not read configuration register on reset
When doing a software reset, the reset flag should be written without
other bits set. Writing the current state will lead to restoring the
state of the PHY (e.g. Powerdown), which is not what is expected from
a software reset.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Michael Welling <mwelling@ieee.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:00 -06:00
Michal Simek
0179063273 net: phy: ti: Enable automatic crossover mode
Enable automatic crossover cable detection.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27 15:55:54 +01:00
Stephen Warren
7c4213f6a5 block: pass block dev not num to read/write/erase()
This will allow the implementation to make use of data in the block_dev
structure beyond the base device number. This will be useful so that eMMC
block devices can encompass the HW partition ID rather than treating this
out-of-band. Equally, the existence of the priv field is crying out for
this patch to exist.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-13 21:05:18 -05:00
Fabio Estevam
d584c68ce0 phy: atheros: Use ar8035_config for AR8031
Commit 08ad9b068a (" ar8031: modify the config func of ar8031 to
ar8021_config") selected 'ar8021_config' as the configuration function
for AR8031.

The correct would be to use 'ar8035_config' instead as AR8031/AR8035
have the same programming model and even share the same phy driver
in the linux kernel: drivers/net/phy/at803x.c.

Tested on a mx6qsabresd and wandboard, which now can work without
any PHY setup code in the board files.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-07 17:46:47 +01:00
Marek Vasut
22854bda80 net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF
Add code to process the KSZ9021/KSZ9031 OF props if they are present
and configure skew registers based on the information from the OF.
This code is only enabled if the DM support for ethernet is also
enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

V2: - Implement struct ksz90x1_reg_field to describe the skew register
      fields more accurately.
    - Fix RXDV/TXEN skew register default value and offset.
2015-12-20 03:36:49 +01:00
Shaohui Xie
f8642ba6dd net: phy: added aquantia PHY AQR405 support
The phy can share driver with other aquantia PHYs, so we only
add PHY ID.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:13 -08:00
Simon Glass
24b852a7a2 Move console definitions into a new console.h file
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:50 -07:00
Edgar E. Iglesias
721aed7912 net: phy: Add support for Texas Instruments DP83867
Code is taken from Linux kernel driver (v4.2).

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-19 13:09:21 +01:00
Vincent BENOIT
5ea667ea2f pengwyn: nand and ethernet fixes
-> Add National instrument ethernet transceiver configuration used (DP83848)
-> Change cpsw slave phy address
-> modify nand configuration to use the correct ECC and correct nand features
2015-11-12 18:13:19 -05:00
Bin Meng
17ecfa9b45 net: phy: Test previous phydev->dev against new mac dev
In phy_connect_dev(), if the phy device has an accociated mac device
before, a warning message will be printed. But we should test the
old device against the new one, if they are actually the same one,
don't print the warning message.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:49 -05:00
Bin Meng
3e1949d774 net: phy: Change to print all phys that are not found
In get_phy_device_by_mask(), when no phy is found, currently we only
print a message to show the first phy address that is not found. But
this is not always the case as multiple phys can be specified by
phy_mask. Change to print all phys that are not found, and to reduce
the console boot log, change to use 'debug' instead of 'printf'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:49 -05:00
Bin Meng
0132b9ab6e net: phy: Don't create phy device when there is no phy
In get_phy_device_by_mask(), when no phy is found, we should not
create any phy device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:48 -05:00
Sylvain Rochet
4f485150cf net: phy: micrel: disable NAND-tree for KSZ8051
NAND-tree is used to check wiring between MAC and PHY using NAND gates
on the PHY side, hence the name.

NAND-tree initial status is latched at reset by probing the IRQ pin.
However some devices are sharing the PHY IRQ pin with other peripherals
such as Atmel SAMA5D[34]x-EK boards when using the optional TM7000
display module, therefore they are switching the PHY in NAND-tree test
mode depending on the current IRQ line status at reset.

This patch ensure PHY is not in NAND-tree test mode only for the Micrel
KSZ8051 PHY used by Atmel. There are other Micrel PHY affected but I
doubt they are used on such weird hardware design.

Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:48 -05:00
Sylvain Lemieux
6617f87668 net: phy: micrel: add support for KSZ8021RNL & KSZ8031RNL
This patch adds support for Micrel KSZ8021RNL & KSZ8031RNL.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:46 -05:00
Mugunthan V N
26d3acdab8 net: phy: on phy device create do not initialize link to 1
Currently when phy device is created the link variable is
initialized to 1 which denoted phy link is already up. On a power
reset there is no issue as phy status register link status will
not be set, so phy auto negotiate will be started. But when a cpu
reset is issued (ex: dra72x-evm) phy's link status bit is already
set which leads to assume that link is already setup in
genphy_update_link() initial check which results in ehternet not
working. So do not assume that link is already up and on phy
device create set link to zero. This is verified on dra72x-evm.

Reported-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-09-29 16:01:29 -05:00
Prabhakar Kushwaha
4c2620dd71 net: phy/vitesse: Add support for VSC8584 phy
Add support of VSC8584 phy placed on new QSGMII/SGMII ethernet riser cards
used on LS2085QDS platforms.

Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:38:39 -05:00
Jiandong Zheng
1b564cecc3 net: phy: broadcom: Add BCM Cygnus PHY
Add Ethernet PHY for BCM Cygnus SoC

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-11 13:49:17 -05:00
Jörg Krause
59370f3fcd net: phy: delay only if reset handler is registered
With commit e3a77218a2 the MII bus is only
reset if a reset handler is registered. If there is no reset handler there
is no need to wait for a device to come out of the reset.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2015-08-11 13:48:25 -05:00
Jörg Krause
2c171a2a5f net: phy: fix data type of phy_id
phy_id is declared as u32 in create_phy_by_mask and in struct phy_device.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2015-08-11 13:47:15 -05:00
Clemens Gruber
8396d0ab8b net: Add support for Marvell 88E1510 PHY
Support the 88E1510 PHY which is very similar to the 88E1518.
I also set the INTn output and configured the LEDs.

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-11 13:29:01 -05:00
Clemens Gruber
90a94ef652 net: Improve 88E151x PHY initialization
- The EEE fixup magic should also be enabled for RGMII
- Improved comments

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-11 13:28:59 -05:00
Shengzhou Liu
90712741c9 net/phy: set led for rtl8211f phy
Initialize LCR rigister to configure
green LED for Link, yellow LED for Active.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-08-11 13:20:34 -05:00
Michal Simek
abbfcbe58e net: phy: Add support for all targets which requires MANUAL_RELOC
Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA
relocation (mostly only GOT) where functions aray are not
updated. This patch is fixing function pointers passed to phy_register
function.
This patch was tested on Microblaze architecture.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-05-19 13:33:21 -05:00
Shengzhou Liu
793ea94770 net/phy: refactor RTL8211F initialization
RTL8211F needs to enalbe TXDLY for RGMII during
phy initialization, so move it to rtl8211f_config
for early initialization.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-05-19 13:33:21 -05:00
Shengzhou Liu
3d6af748eb net/phy: Add support for realtek RTL8211F
RTL8211F has different registers from RTL8211E.
This patch adds support for RTL8211F PHY which
can be found on Freescale's T1023 RDB board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-05-19 13:33:20 -05:00
pankaj chauhan
8bb065630f net/phy/cortina: Fix compilation warning
Fix comilation warning which is emitted when
firmware address is more than 32 bit.

Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:57 -07:00
Shengzhou Liu
5707d5ffd4 net/phy: fixup for get_phy_id
commit 3c6928fd7b "net: phy: fix warnings with W=1" caused
some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the
warning and make those special PHYs working as well.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-04-20 17:57:13 -05:00
Luca Ellero
c6a40f6e51 net: phy: micrel: add support for KSZ8081MNX
This patch adds a support for KSZ8081MNX in MII mode.

Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
Acked-by: Pavel Machek <pavel@denx.de>
2015-04-20 17:57:12 -05:00
Codrin Ciubotariu
3cee138892 net: phy: realtek: Disable interrupt on Realtek Ethernet PHY drivers
Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have
interrupts enabled by default. If the interrupt is not treated later by
the OS and the PHY's interrupt line is enabled and shared with other
interrupts, the system will get an interrupt storm. This patch disables
the interrupt for PHY devices that use one of the current Realtek
Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L)
have the interrupt masked. In this case, the functionality of the PHY
should not be afected since this patch brings INER and INSR registers to
their default values.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-20 17:57:11 -05:00
Simon Glass
c74c8e6651 dm: net: Adjust PHY interface to work with CONFIG_DM_ETH
When driver model is used for Ethernet a few functions are passed a udevice
instead of an eth_device. Also add a function to find a PHY type given its
name. This will be used to decode the device tree node.

Finally, put a phy_interface field in struct eth_pdata since this is an
important part of the platform data for Ethernet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-18 11:11:36 -06:00
Philippe De Muyter
b7a5b08438 net: phy: micrel: add support for KSZ8895 switch in SMI mode
This patch adds a phy driver for the Micrel KSZ8895 switch.  As the SoC MAC
is directly connected to the switch MAC the link to the switch is always up.

But the KSZ8895 switch can be hardwired in three configuration modes :
- not configurable with eventually an eeprom-stored configuration
- configurable by the mdio/mdc connection (SMI protocol)
- configurable by a SPI connection.

In not configurable mode, the switch starts automatically, but in the
other modes, it must be started programmatically, by writing 1 in
configuration register 1.
We only support the not configurable and mdio/mdc (aka SMI) modes here.

Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2015-01-30 15:55:00 -06:00
Shaohui Xie
f7c38cf827 phylib: add support for aquantia PHYs
This patch supports AQ1202, AQ2104, AQR105 PHY.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:32:11 -08:00
Shengzhou Liu
c18fc2c960 net/phy: enable serdes auto-negotiation for vsc8514 phy
VSC8514 QSGMII PHY requires enabling auto-negotiation,
otherwise it wouldn't work.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
9b18e5199e net/phy: Add support for CS4315/CS4340 PHY
Add support for Cortina CS4315/CS4340 10G PHY.
- This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
  to initialize Cortina PHY.
- Cortina PHY has non-standard offset of PHY ID registers, thus
  we define own get_phy_id() to override default get_phy_id().
- To define macro CONFIG_PHY_CORTINA will enable this driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:11 -08:00
Hao Zhang
35fa0dda0c net: phy: marvell: add errata w/a for 88E151* chips
As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514
Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires
that certain registers get written in order to restart
autonegotiation.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-11-06 11:04:38 -05:00
Tom Rini
5aa7bece10 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-10-27 09:05:43 -04:00
Jeroen Hofstee
3c6928fd7b net: phy: fix warnings with W=1
get_phy_id is marked weak but has no protype nor a
strong version, just make it static. Use __weak for
board_phy_config.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 07:01:59 -04:00
Khoronzhuk, Ivan
adc9a79f3f net: phy: print a number of phy that is not found
In case when several Ethernet ports are supported it's
convenient to see the number of phy that is not found.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Pavel Machek
58ec63d6bc net: phy: Cleanup drivers/net/phy/micrel.c
Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Chin Liang See <clsee@altera.com>
2014-10-06 17:36:40 +02:00
Masahiro Yamada
368b4d2b49 drivers: net: remove dead drivers
The following configs are not defined at all:

 - CONFIG_INCA_IP_SWITCH
 - CONFIG_PBL2800_ETHER
 - CONFIG_PHY_ICPLUS

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:11 -04:00
maxin.john@enea.com
79e86ccb37 vitesse: remove duplicated argument to ||
Remove the duplicated argument to || check

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-08-09 11:17:02 -04:00
Cormier, Jonathan
08be2836df phy: fix create_phy_by_mask for when its given an actual search mask
get_phy_id returns -EIO when it can't read from a phy at a given addr.  This would cause
create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask.

Example usage:
Replace
    phydev = phy_connect(bus, phy_addr, dev, phy_if)
with
    phydev = phy_find_by_mask(bus, phy_mask, phy_if)
    if (phydev)
	phy_connect_dev(phydev, dev);

Signed-off-by: Cormier, Jonathan <jcormier@criticallink.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
2014-06-05 14:44:56 -04:00
Chunhe Lan
ffc8667acf net: phy/vitesse: Add support for VSC8664 phy module
This patch adds support for VSC8664 PHY module which can
be found on Freescale's T4240RDB boards.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:05 -05:00
Shengzhou Liu
597fe041a8 net/phy: enable get_phy_id redefinable
As some PHYs have non-standard PHY ID registers, PHY Id can't
be read correctly by current get_phy_id function, so we enable
get_phy_id redefinable to permit specific PHY driver having own
specific get_phy_id function.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-05-12 15:19:45 -04:00
Xiaobo Xie
02aa4c5388 AR8035/phy: Enable autonegotiation function for ar8035
Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before,
but used "if (phydev->supported & SUPPORTED_Autoneg)" now.
So assign "phydev->supported" to "phydev->drv->features" for ar8035
to enable autonegotiation. Then removed the genphy_config_aneg() function.

Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2014-05-12 15:19:45 -04:00
Zhao Qiang
08ad9b068a ar8031: modify the config func of ar8031 to ar8021_config
ar8031 has the same config steps with ar8021, so change its
config func to ar8021_config instead of genphy_config.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:53 -07:00
Codrin Ciubotariu
44afbbc0f0 net/phy: Fix PHY id for VSC8514
In the current Datasheet for VSC8514 there is a mistake, saying that
the PHY id is 0x70570. The real value in the identifier registers is
0x70670. Linux PHY driver uses 0x70670 also.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Haijun.Zhang
dc116bd6c4 net/phy: Correct AR8021 phy_mask
There was wrong phy_mask for AR8021 device,
so the AR8021 can't be probed correctly.
Changed it from 0x4fffff to 0x4ffff0.

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
2014-03-07 10:59:06 -05:00
Tom Rini
a7e8c15f71 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-25 13:55:49 -05:00
Zhao Qiang
e0d809647f ar8031/8033/phy:enable autonegotiation for ar8031/8033
Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before
while "if (phydev->supported & SUPPORTED_Autoneg)" now.
So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033
to enable autonegotiation.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:23:41 -08:00
Heiko Schocher
9137d19bdd net, phy: atheros ar803x bug
commit 626ee1e3 "phylib: update atheros ar803x phy"

leads in failing ethernet on the pxm2 board.

Calling genphy_config() instead of ar8021_config(),
which seems for ar8021 phys not ar803x phys, make
it working again.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
2014-02-19 10:47:33 -05:00
Fabio Estevam
f66e3ded61 net: phy: atheros: Fix the masks for AR8031/8035
Use the same masks as used in the kernel:
https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6

With such changes Ethernet is functional on hummingboard solo.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Marek Vasut <marex@denx.de>
Patch: 306640
2014-01-14 14:00:41 -06:00
David Dueck
f27f3b5266 phy: Use general phy code for smsc lan8720a
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
2013-11-22 17:03:20 -06:00
David Dueck
3a530d1b3e phy: Use supported field during autonegotiation
The current code incorrectly detects gigabit capabilities for some
100Mbit/s phys. (lan8720a)

Signed-off-by: David Dueck <davidcdueck@googlemail.com>
2013-11-22 17:03:20 -06:00
Fabio Estevam
e003ba5bfc net: phy: atheros: Fix masks for AR8035 and AR8021
The masks were ignoring the last 4 bits which didn't allow detection differences
between the ar8031 and ar8035.

Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Patch: 288018
2013-11-22 17:03:18 -06:00
Chunhe Lan
3177457853 net/phy: Fix the phy id mask of AR8031
The both AR8031 and AR8035 belong to Atheros 803x serial PHY.
So the phy id mask of AR8031 is the same to the phy id mask
of AR8035. The right mask value is 0x4fffff.

This patch has been tested on the P1010 and P1023.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 287748
2013-11-22 17:03:18 -06:00
Heiko Schocher
dfcaa61c33 net, phy: fix AR8031 phy_mask
AR8035 driver will be never applied because of wrong mask for
AR8031 driver. Fix this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 276944
2013-11-22 16:50:54 -06:00
Stefano Babic
9ced16fefa net: add function to read/write extended registers in Micrel Phy
Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:52 -06:00
Stefano Babic
e8194d58bd net: fix mask for phy Micrel KSZ9031
Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:51 -06:00