No intended functional change, just remove redundancies in some
Makefiles, and make whitespace aesthetics uniform.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For malloc to work in SPL framework enable GD_FLG_FULL_MALLOC_INIT
flag in global data after allocating memory using mem_malloc_init.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
These functions are part of the Linux 4.6 sync. They are being added
before the main sync patch in order to make it easier to address the
issue across all NAND drivers (many/most of which do not closely track
their Linux counterparts) separately from other merge issues.
Signed-off-by: Scott Wood <oss@buserror.net>
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc
Also move README.lsch2 and README.lsch3 in same folder.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should
be used for USB 3 & 2.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS102A ref manual dictates that ICID have to be written to the MSB
of the ICID register, not to the LSB.
Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT:
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
depends on OF_LIBFDT
...
remove superfluous tests of CONFIG_OF_LIBFDT when testing for
CONFIG_OF_BOARD_SETUP.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Typo fix: s/ifdefi/ifdef/]
Signed-off-by: Tom Rini <trini@konsulko.com>
Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5,
FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6.
Signed-off-by: Ying Zhang <ying.zhang22455@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity
by setting relative bit in SCFG_INTPCR register, because AQR105
interrupt is low active but GIC accepts high active.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Some SOCs, specifically the ones in the C29x familiy can have
multiple security engines. This patch adds a system configuration
define which indicates the maximum number of SEC engines that
can be found on a SoC.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
gd->env_addr will be initialized in env_init() in
common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined.
So no need to do it again.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Mix usage of uint32_t and u32 fixed in favor of u32.
Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: York Sun <york.sun@nxp.com>
On the LS102x boards, in order to initialize the ICID values of
masters, the dev_stream_id array holds absolute offsets from the
base of SCFG.
In ls102xa_config_ssmu_stream_id, the base pointer is cast to
uint32_t * before adding the offset, leading to an invalid address.
Casting it to void * solves the issue.
Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Optimize DDR timing for good margins to support new Transcend
and Apacer DDR4 UDIMM besides current Micron UDIMM.
Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with
following UDIMM on LS2080ARDB.
- Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
- Apacer UDIMM: 78.C1GM4.AF10B
- Transcend UDIMM: TS1GLH72V1H
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
When setting fixed-link property to DTS, the values should be converted
with using cpu_to_fdt32 so that to have correct value on little endian
Soc.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Having had a similar board and memory part under logic analyzer, a
tINIT3 violation was measured. The fix was involved keeping tXPR and
SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC
value for LPDDR2. There was also a tIH-CA violation and this was
resolved by writing the default value in rather than what the script
here uses.
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Having had a similar board and memory part under logic analyzer, a
tINIT3 violation was measured. The fix was involved keeping tXPR and
SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC
value for LPDDR2.
Cc: Jason Liu <jason.hui.liu@nxp.com>
Cc: Ye Li <ye.li@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
enable_lvds() function only set bits IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT and
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT, but these bits were already set
previously inside setup_display().
We can safely remove enable_lvds() then.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.
This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Use a pointer to pass image address to fsl_secboot_validate(),
instead of using environmental variable "img_addr".
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In case of fatal failure during secure boot execution (e.g. header
not found), reset is asserted to stop execution. If the RESET_REQ
is not tied to HRESET, this allows the execution to continue.
Add esbh_halt() after the reset to make sure execution stops.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.
Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
VESA 1024x768 results in much more accurate timings.
Based on the patch from Soeren Moch for the tbs2910 board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
The fsl-mc node has been moved under /soc, so update
the path references accordingly. Backwards compatibility
is retained for /fsl-mc.
Delete backwards compatibility for the completely obsolete
/fsl,dprc@0.
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Return i2c mux to the default channel after accessing retimer.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
IR chip is on one of the channels on multiplexed I2C-bus.
Reset to default channel after accessing.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As phy_connect and phy_config are being called from DPAA2 driver.
Remove calling of mentioned function from board file.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
