commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.
The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
commit ab9240402a70cc02496683971779e75eff410ab4 upstream.
- function mv_ddr_spd_die_capacity_user_get() has a bug,
since it insert a user memory enum to it,
instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32 bit already calculated correctly
at mv_ddr_mem_sz_per_cs_get() function
Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Stefan Chulski <Stefan.Chulski@cavium.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.
Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.
Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
commit a165037ec26f301be75e1fabc263643683e85255 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.
- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
then the algorithm will fail, since it think that there are no phase to correct
Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
The SPI NOR flash node name in main device tree for Turris Omnia is
called `spi-nor@0`.
Rename node spi-flash@0 in Turris Omnia's -u-boot.dtsi file to spi-nor@0
so that U-Boot does not try to probe the same SPI NOR device multiple
times.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
Linux displays the real PCIe card connected to a mvebu PCIe slot as
device 0, not 1. This is done by setting local dev number to 1, so that
the local "Marvell Memory controller" device is on address 1.
Let's do it also in U-Boot.
With this commit the pci command in U-Boot prints something like:
=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x168c 0x003c Network controller 0x80
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Refactor validation of bdf parameter in mvebu_pcie_read/write_config
functions.
We can simplify the code by putting the validation into separate
function.
Also there are always only two devices visible on local bus:
* on slot configured by function mvebu_pcie_set_local_dev_nr()
(by default this register is set to 0) there is a
"Marvell Memory controller", which isn't useful in root complex
mode,
* on all other slots the real PCIe card connected to the PCIe slot.
We can simplify the code even more by simply allowing access only to
the real PCIe card.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when
debugging is enabled. Print size for pci_mvebu as well.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Write bdf address in a same way in mvebu_pcie_read/write_config.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
PCI uclass maps PCI bus numbers to the seq member of struct udevice.
Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an
incrementing a static variable.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
NVMe drives can be connected to Turris MOX via MOX B and MOX G
extensions.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
USB devices can be connected to Turris MOX also via MOX F extension which
contains VL805 PCIe based USB 3.0 controller.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
PCIe devices do not work in U-Boot without proper initialization and
configuration of PCI config space like the PCI_BASE_ADDRESS_0 register.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to
Armada 3720 SOC. Without this U-Boot crashes when trying to access
enumerated USB devices connected to this XHCI PCIe controller.
This should be done according to the PCIe Link Initialization sequence, as
defined in Marvell Armada 3720 Functional Specification.
Linux has this code too.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
The NOR flash w25q128 denoted by JEDEC ID 0xef4018 actually represents
various models. From Winbond's website, I could only find 3 types of
them:
W25Q128JV-IQ/JQ
datasheet:https://www.winbond.com/resource-files/
w25q128jv%20revg%2004082019%20plus.pdf
W25Q128FV (SPI Mode)
datasheet: https://www.winbond.com/resource-files/
w25q128fv%20rev.m%2005132016%20kms.pdf
W25Q128BV
datesheet: https://www.winbond.com/resource-files/
w25q128bv_revh_100313_wo_automotive.pdf
According to the datasheets, all of these 3 types support BP(0,1,2) and
TB bits in the status register (SR), so it could reuse the flash
protection logic for ST Micro.
So it should be safe to add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
flags to the w25q128 entry of spi_nor_ids table.
Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[jagan: remove comments in spi-nor-ids.c]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The set_speed() callback should configure the bus speed, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it. As this is the last ARCH_MPC8569 board, remove that support
as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
In the cases of T2080RDB_SECURE_BOOT, T2080RDB_SRIO_PCIE_BOOT,
P2041RDB_SECURE_BOOT, P2041RDB_SRIO_PCIE_BOOT, P3041DS_SRIO_PCIE_BOOT
and P4080DS_SRIO_PCIE_BOOT while some forms of the board have been
migrated more fully to current build standards, these have not. Remove
them.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This device has four IOs connected to the SPI flash. Add the appropriate
bindings.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Let the sbi command detect the 'System Reset Extension'
(EID #0x53525354 "SRST").
Cf. https://github.com/riscv/riscv-sbi-doc
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Commit "common: Drop asm/global_data.h from common header" added
asm/global_data.h into secure.h. However, secure.h will be included
by psci.S. Adding asm/global_data.h has caused compilation failure in
pcsi.S. Add "ifndef __ASSEMBLY__" in asm/global_data.h.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When copying to a u32 field we should use sizeof(u32) and not
sizeof(*u32) in memcpy.
On 64bit systems like cortina_presidio-asic-emmc_defconfig using
sizeof(*u32) leads to a buffer overrun.
Fixes: febe13b438 ("net: cortina_ni: Add eth support for Cortina Access CAxxxx SoCs")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
ca_do_bch_correction() takes a random value from the stack and starts
counting bitflips from this value. Initialize the counter.
This passed unnoticed as the value is finally ignored in the call
hierarchy.
Fixes: 161df94b3c ("mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The values of left_edge[0] and right_edge[0] are overwritten before they
are used. Remove the superfluous assignments.
Fixes: 285b3cb939 ("dm: ddr: socfpga: fix gen5 ddr driver to not use bss")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Include "compiler.h" in sha512.c. This is needed by 'cpu_to_be64' macro
that used in 'sha512_base_do_finalize' function.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In 8a8d24bd Simon dropped data from all the various _platdata calls
but it seems this wasn't caught for the RNG200 driver from when it
was posted to merged. This fixes that issue.
Fixes: 537f0018 (rng: Add iProc RNG200 driver)
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
test/cmd/setexpr.c cannot be linked with CONFIG_CMD_SETEXPR=n:
ld.bfd: test/built-in.o: in function `setexpr_test_sub':
test/cmd/setexpr.c:227: undefined reference to `setexpr_regex_sub'
ld.bfd: test/built-in.o: in function `setexpr_test_backref':
test/cmd/setexpr.c:267: undefined reference to `setexpr_regex_sub'
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Avoid build warnings observed with gcc 10.2
In file included from lib/rsa/rsa-keyprop.c:16:
include/u-boot/rsa-mod-exp.h:65:24: warning:
‘struct udevice’ declared inside parameter list will not be visible
outside of this definition or declaration
65 | int rsa_mod_exp(struct udevice *dev, const uint8_t *sig,
| uint32_t sig_len,
| ^~~~~~~
include/u-boot/rsa-mod-exp.h:96:24: warning:
‘struct udevice’ declared inside parameter list will not be visible
outside of this definition or declaration
96 | int (*mod_exp)(struct udevice *dev, const uint8_t *sig,
|
by defining struct udevice.
Fixes: 401d1c4f5d ("common: Drop asm/global_data.h from common header")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The EFI Grub workaround on BananaPi R2 slows down the boot process to
the point, that the watchdog will trigger a reboot before the kernel can
reset it. Fix this by disabeling the workaround.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Currently we fail silently if there is an algorithm mismatch. To help
distinguish this failure condition.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
VIRTIO_ID_MAX_NUM is the largest device ID plus 1. Therefore a device id
cannot be greater or equal to VIRTIO_ID_MAX_NUM. Fix the comparison
accordingly.
Fixes: 8fb49b4c7a ("dm: Add a new uclass driver for VirtIO transport devices")
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Current sed usage in the DTC command relies on GNU sed specific -i
option which has a slightly different syntax for BSD sed and always
expects an extension to be provided in order to create a backup file.
Instead drop the cat concatenation done before the sed call and use
sed itself to edit and concatenate the files.
No functional change intended.
Signed-off-by: Roger Pau Monné <royger@FreeBSD.org>
Fist use extended regexp in order to drop the '\' around the
parentheses which is not supported by BSD sed in regular mode.
Secondly use [[:blank:]] instead of \s, as the later is a GNU
extension.
No functional change intended.
Signed-off-by: Roger Pau Monné <royger@FreeBSD.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Compiling the sandbox fails on armv7 due to conflicting definitions of
memcpy() and memset() in include/malloc.h and include/linux/string.h.
Use linux/string.h here.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the hikey to use DM_USB and DM_ETH.
Conversion based on rpi as it has a similar DWC config.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
