Commit graph

7417 commits

Author SHA1 Message Date
Tom Rini
d7ac865b98 Merge git://source.denx.de/u-boot-socfpga
Bugfixes for this one socfpga platform
2021-09-23 08:30:45 -04:00
Marek Vasut
cb3ed86cf1 arm: socfpga: vining: Enable DW I2C driver
The Designware I2C IP is used to communicate with I2C peripherals on
SoCFPGA, and required to access I2C EEPROM on this board. Enable it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22 21:30:39 +02:00
Marek Vasut
4e106ef9ef arm: socfpga: vining: Set default SPI NOR mode and frequency
The SPI NOR bus mode is 0 on this system, update it accordingly.
Increase frequency to 40 MHz and enable SFDP parsing, since the
flashes on this system support that and it is a huge performance
improvement.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22 21:30:39 +02:00
Marek Vasut
3cb04b895d arm: socfpga: vining: Set USB gadget manufacturer to Softing with capital S
This was configured in downstream, so it is likely that most of the
custom software used around the device depends on it. Make upstream
compatible.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22 21:30:39 +02:00
Marek Vasut
513f7d1c5d arm: socfpga: vining: Increase environment size
Increase the environment size from 4k to 16k to prevent
environment from becoming full.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22 21:30:39 +02:00
Samuel Holland
672ee240d9 configs: Enable USB3 on Allwinner H6 boards
Pine H64 and Orange Pi 3 both provide a USB3 type A port.
Enable it in U-Boot.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-22 21:29:56 +02:00
Matthias Brugger
1bc00bc74b configs: rpi: Enable SMBIOS sysinfo driver
Enable this driver to allow U-Boot to get SMBIOS table information from
a device tree node.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Fabian Vogt <fvogt@suse.com>
2021-09-15 12:29:53 +02:00
Tom Rini
e3e2c6430b configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-14 18:48:05 -04:00
Simon Glass
46596c653b ppc: Remove UCP1020 board
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.

Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt
because it's not really migrated at this point.

Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-13 18:22:50 -04:00
Aswath Govindraju
cab1306a09 configs: j72*_evm: Define the buffer sizes for dfu
On J721e R5 SPL, dfu buffer for loading sysfw.itb image gets allocated
before DRAM gets initialized. So, the buffer gets allocated in MCU L3
RAM. The current buffer size to be allocated is 256KB  and the available
total heap memory is 0x70000 (448KB). This leads to NOMEM errors during
allocation.

In other cases when constraints such as above are not present fix the size
of buffers to the sector size in OSPI for proper functioning.

Also, if CONFIG_SYS_DFU_DATA_BUF_SIZE is defined and
CONFIG_SYS_DFU_MAX_FILE_SIZE is not defined then the max file size for dfu
transfer is defined as CONFIG_SYS_DFU_DATA_BUF_SIZE.

Fix these by setting appropriate buffer sizes in their respective defconfig
files and defining the max file size as 8 MB which is the default dfu
buffer size.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-09-10 20:10:20 -04:00
Derald D. Woods
11e2ab3f0b ARM: omap3: evm: Enable booting 'fitImage' with DEFAULT_FIT_TI_ARGS
This commit uses the existing DEFAULT_MMC_TI_ARGS and
DEFAULT_FIT_TI_ARGS defintions to replace the 'mmc*' environment
variables in the configuration. The check for the 'boot_fit' is handled
like the 'am335x_*' boards with 'CONFIG_BOOTCOMMAND'.

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
2021-09-10 18:00:37 -04:00
Tom Rini
f4b64e9736 arm: am335x: Enable SPL_OF_CONTROL on some configs
Both am335x_boneblack_vboot and am335x_evm_spiboot require
SPL_OF_CONTROL to function but are currently missing this option.  Add
it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-10 18:00:37 -04:00
Pali Rohár
5a8bd463a6 arm: mvebu: espressobin: Enable GPT partition support
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 09:01:51 +02:00
Pali Rohár
f4ce28ab74 arm: mvebu: turris_{omnia, mox}: GPT partition support
This allows U-Boot to access filesystems on GPT partitioned disks.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 09:01:51 +02:00
Alexandru Gagniuc
0721209699 common/spl: Drop [ST]PL_HASH_SUPPORT in favor of [ST]PL_HASH
All of these configs exist. Stick to using CONFIG_[ST]PL_HASH, and drop all
references to CONFIG_[ST]PL_HASH_SUPPORT.  This means we need for
CHAIN_OF_TRUST to select SPL_HASH now.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Add TPL case, fix CHAIN_OF_TRUST, other tweaks]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-08 16:11:46 -04:00
Alexandru Gagniuc
eb5171ddec common: Remove unused CONFIG_FIT_SHAxxx selectors
Originally CONFIG_FIT_SHAxxx enabled specific SHA algos for and only
for hash_calculate() in common/image-fit.c. However, since commit
14f061dcb1 ("image: Drop IMAGE_ENABLE_SHAxxx"),
the correct selector was changed to CONFIG_SHAxxx.

The extra "_FIT_" variants are neither used, nor needed. Remove them.
One defconfig disables FIT_SHA256, which is now changed to 'SHA256'.

CMD_MVEBU_BUBT needs to select select SHA256 to avoid undefined
references to "sha256_*()". bubt.c needs sha256, so this selection is
correct. It is not clear why this problem did not manifest before.

Note that SHA selection in SPL is broken for this exact reason. There
is no corresponding SPL_SHAxxx. Fixing this is is beyond the scope of
this change.

Also note that we make CONFIG_FIT now imply SHA256, to make up for
FIT_SHA256 previously being a default y option.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Add imply SHA256 to FIT]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-08 16:10:34 -04:00
Heinrich Schuchardt
5b2d359d9a configs: qemu-riscvXX_spl_defconfig enable CMD_SBI
Both for 64bit and 32bit at least on one board we should compile the sbi
command. Enabling it on QEMU will allow to write a test for it.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-07 10:34:29 +08:00
Heinrich Schuchardt
7383432fa1 riscv: enable booting HiFive Unmatched from SATA
On the HiFive Unmatched a PCI to SATA adapter may be used to install a SATA
drive. Enable booting from it.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2021-09-07 10:34:28 +08:00
Marek Behún
aeb0ca64db arm: mvebu: turris_omnia: disable MCU watchdog in SPL when booting over UART
When booting over UART, sending U-Boot proper may take too much time and
MCU watchdog will reset the board before U-Boot proper is loaded.

Better disable MCU watchdog in SPL when booting over UART.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-01 08:09:24 +02:00
Pali Rohár
167689897b serial: a37xx: Remove CONFIG_DEBUG_UART_SHIFT options
Armada 37xx serial driver does not use CONFIG_DEBUG_UART_SHIFT.

So do not define any bogus value for CONFIG_DEBUG_UART_SHIFT option in any
Armada 37xx defconfig file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-01 08:07:04 +02:00
Pali Rohár
1b713f1550 arm: mvebu: turris_omnia: Enable NVMe support
PCIe-based NVMe SSD disks in M.2 2230/2242/2260 form-factor can be
connected to Turris Omnia mPCIe slot via passive M.2 <--> mPCIe adapter.

So enable PCIe NVMe drivers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-01 08:07:04 +02:00
Pali Rohár
be575083c9 arm: mvebu: turris_mox: Enable SATA support
SATA disks could be connected via mPCIe add-in card with PCIe-SATA
controller into Mox-B or Mox-G module.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-01 08:07:04 +02:00
Pali Rohár
8e7fe46305 arm: mvebu: espressobin: Enable also SATA support via PCIe
Espressobin has one on-board SATA port which is connected directly to CPU.

More SATA disks can be connected via mPCIe add-in card with PCIe-SATA
controller.

So enable required SATA AHCI PCIe drivers in defconfig file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-01 08:07:04 +02:00
Tom Rini
b15a17be0c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh 2021-08-31 18:37:25 -04:00
Tom Rini
18f528535d configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 12:40:24 -04:00
Tom Rini
b9cb74a5aa Xilinx changes for v2021.10-rc3
xilinx:
 - Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
 - Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
 - Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT
 
 zynq:
 - Wire single QSPI
 - Use power-source instead of io-standard properties
 - Enable nor on zc770-xm012
 
 zynqmp:
 - Change handling around multi_boot()
 - Setup offset for u-boot.itb in spi
 - Generate run time dfu_alt_info for capsule update
 - Use explicit values for enums (zynqmp_firmware.h)
 - Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
 - Disable WDT driver by default
 - Bind usb/scsi via preboot because of EFI
 - DT updates/fixes
 - Add soc driver
 - Fix SPL SPI boot mode
 
 versal:
 - Add soc driver
 
 sdhci:
 - Update tap delay programming for zynq_sdhci driver
 
 cmd:
 - Fix RTC uclass handling in date command
 - Update pwm help message
 - Update reset help message
 
 watchdog:
 - Fix wwdt compilation
 
 rtc:
 - Deal with seq alias in rtc uclass
 - Add zynqmp RTC driver
 
 fdt:
 - Add kernel-doc for fdt_fixup_memory_banks()
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Merge tag 'xilinx-for-v2021.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.10-rc3

xilinx:
- Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
- Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
- Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT

zynq:
- Wire single QSPI
- Use power-source instead of io-standard properties
- Enable nor on zc770-xm012

zynqmp:
- Change handling around multi_boot()
- Setup offset for u-boot.itb in spi
- Generate run time dfu_alt_info for capsule update
- Use explicit values for enums (zynqmp_firmware.h)
- Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
- Disable WDT driver by default
- Bind usb/scsi via preboot because of EFI
- DT updates/fixes
- Add soc driver
- Fix SPL SPI boot mode

versal:
- Add soc driver

sdhci:
- Update tap delay programming for zynq_sdhci driver

cmd:
- Fix RTC uclass handling in date command
- Update pwm help message
- Update reset help message

watchdog:
- Fix wwdt compilation

rtc:
- Deal with seq alias in rtc uclass
- Add zynqmp RTC driver

fdt:
- Add kernel-doc for fdt_fixup_memory_banks()
2021-08-27 08:33:02 -04:00
Michal Simek
229cb5c6ba xilinx: zynqmp: Enable stack relocation to DDR
There is no space in OCM for SPL stack because the space in OCM is occupied
by TF-A. That's why move relocate stack to DDR to 0x18000000 address
and also enable SPL_SIZE_LIMIT not to be more then 0xfffea000 which is
default address for TFA.

It is good to summarize current DDR usage in SPL flow.
0-0x80000 is used for BSS
 (CONFIG_SPL_BSS_START_ADDR, CONFIG_SPL_BSS_MAX_SIZE)
0x100000 is used for DTB passing address
 (CONFIG_XILINX_OF_BOARD_DTB_ADDR)
0x17fffe70 - CONFIG_SPL_STACK_R_ADDR - is used for GD
0x18000000 is used for SPL stack
 (CONFIG_SPL_STACK_R_ADDR)
0x20000000-0x21000000 is used for SPL malloc area
 (CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
edd530651a xilinx: zynqmp: Enable gpio-key/button driver
Enable button uclass and also gpio-key driver by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:12:56 +02:00
Michal Simek
57bcae88fe arm64: zynqmp: Enable sha1sum command
Enable it for TPM usage.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
57b2a43607 xilinx: Enable config to display cpuinfo
Enable CONFIG_DISPLAY_CPUINFO to display SoC family & revision.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
42e20f52d9 soc: xilinx: versal: Add soc_xilinx_versal driver
soc_xilinx_versal driver allows identification of family & revision
of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL.
Probe this driver using platdata U_BOOT_DEVICE structure which is
defined at mach-versal/cpu.c.
Add this config to xilinx_versal_virt_defconfig &
xilinx_versal_mini_ospi_defconfig file to select this driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
a890a53ad2 soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver
soc_xilinx_zynqmp driver allows identification of family & revision
of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP.
Add this config to xilinx_zynqmp_virt_defconfig file.
Probe this driver using platdata U_BOOT_DEVICE structure which is
specified in mach-zynqmp/cpu.c.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
1031a11d71 xilinx: Disable ARCH_FIXUP_FDT_MEMORY
Based on DT spec you can have one memory node which multiple ranges or
multiple nodes.
fdt_fixup_memory_banks() is not implemented in a correct way when multiple
memory nodes are present because all ranges are put it to the first memory
node found. And next memory nodes are kept in DT which ends up in the same
range specification in the same DT.

Here is what it is happening.
Origin DT.
memory@0 {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x80000000>;
};

memory@800000000 {
        device_type = "memory";
        reg = <0x8 0x00000000 0x0 0x80000000>;
};

After fdt_fixup_memory_banks()

memory@0 {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};

memory@800000000 {
        device_type = "memory";
        reg = <0x8 0x00000000 0x0 0x80000000>;
};

As is visible memory@0 node got second range but there is still
memory@800000000 node present and 2G range is listed twice.

The solution can't be that second node is removed because it can be
referenced already that's why it is better for us to disable this option
for now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
18bfe9cf5a xilinx: zynqmp: Initialize usb and scsi via preboot
Based on thread
https://lists.denx.de/pipermail/u-boot/2021-June/451828.html
especially
"Overall we have a deficiency in the UEFI implementation in that we
cannot deal with block devices added or removed after initialization."
there is a need to deal with removable media as usb/scsi/sata.

That's why bridge this gap in EFI implementation by resetting usb and
scsi resets to get all disks before efi_init_obj_list() is called.

In our standard boot flow, where we use distro boot, order is fixed as
"jtag mmc0 mmc1 qspi0 nand0 usb0 usb1 scsi0 pxe dhcp" with prioritizing
boot device added by commit 2882b39d56 ("arm64: zynqmp: Setup the first
boot_target at run time").
When device has ESP partition all devices should be detected because then
efi_disk_register() in efi_init_obj_list() is called only once.

The first such a device is sd/emmc(mmc0/mmc1) and then disks on usb/sata
are not handled at all.

The commit 6bb577dbb3 ("arm64: zynqmp: Disable
EFI_CAPSULE_ON_DISK_EARLY") also pointed out on this issue but detection of
removable media wasn't solved that's why do it now via preboot command.

I have tested cases without usb and scsi and there is no problem with
calling resets without devices itself.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
055dfdc257 arm64: zynqmp: Disable WDT_CDNS driver by default
Do not enable watchdog driver in default zynqmp configuration. The reason
is that not all distributions are handling watchdog properly and then
expires and system resets. If someone needs watchdog in their design please
enable it by hand.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Siew Chin Lim
31b51cb1d2 arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25 15:26:38 +08:00
Adam Ford
221146c558 ARM: rmobile: beacon-renesom: Enable QSPI NOR Flash
There is a QSPI NOR flash part on the board.  Because this chip isn't
yet supported in Linux, but it is supported in U-Boot, and the
face that the RPC_SPI compatible names are different in U-Boot and
Linux, the device tree updates are confined to -u-boot.dtsi files.

In order to use the QSPI, TF-A must leave RPC unlocked by compiling
TF-A with RZG_RPC_HYPERFLASH_LOCKED=0.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Biju Bas <biju.das.jz@bp.renesas.com>
2021-08-24 20:03:09 +02:00
Siew Chin Lim
510c277a2e arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.

U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24 14:29:50 +08:00
Tom Rini
18f4e85876 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
fsl-qoriq: Fixes related to env, spi, usb, crypto, configs, distro-boot
for Layerscape Boards like lx2, sl28, ls2088ardb.
powerpc: Fixes for t208xrdb revd board and cortina related configs
update for T208xRDB, T4240RDB.
2021-08-23 09:17:32 -04:00
Nandor Han
c50b21b705 bootcount: add a new driver with syscon as backend
The driver will use a syscon regmap as backend and supports both
16 and 32 size value. The value will be stored in the CPU's endianness.

Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-22 11:04:52 +02:00
Kuldeep Singh
e99b1dfcb7 configs: Migrate CORTINA_FW_ADDR and CORTINA_FW_LENGTH to Kconfig
Use moveconfig.py script to convert below defines to Kconfig and move
these entries to defconfigs.
    CONFIG_CORTINA_FW_ADDR
    CONFIG_CORTINA_FW_LENGTH

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18 15:55:15 +05:30
Kuldeep Singh
00ac37a9bc lx2160a: Enable CONFIG_SPI_FLASH_MT35XU for lx2160a-rdb/qds
LX2160A-RDB/QDS has micron mt35xu512aba flash which requires flag
CONFIG_SPI_FLASH_MT35XU on to probe flash successfully.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18 15:55:15 +05:30
Dimitri John Ledkov
8359fd7313 qemu-riscv64_smode: fix extlinux (define preboot)
Commit 37304aaf60 ("Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to
Kconfig") removed preboot commands in RISC-V targets and broke
extlinux support as reported by Fu Wei <wefu@redhat.com>.

The patch finishes migration of CONFIG_USE_PREBOOT and CONFIG_REBOOT
to Kconfig.

Fixes: 37304aaf60 ("Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to Kconfig")
Reported-By: Fu Wei <wefu@redhat.com>
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Dimitri John Ledkov <dimitri.ledkov@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-08-17 19:28:37 +08:00
Tom Rini
4edc79b016 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-16 09:35:24 -04:00
Alexandru Gagniuc
46a738a4ec test: dm: Add test for ECDSA UCLASS support
This test verifies that ECDSA_UCLASS is implemented, and that
ecdsa_verify() works as expected. The definition of "expected" is
"does not find a device, and returns -ENODEV".

The lack of a hardware-independent ECDSA implementation prevents us
from having one in the sandbox, for now.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-08-16 10:49:35 +02:00
Marek Vasut
df68620743 ARM: stm32: Set environment sector size to 4k on DHSOM
The DHSOM SPI NOR is using 4k erase blocks, make use of it
and define the default environment sector size to 4k.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-16 10:49:35 +02:00
Patrick Delaunay
b73e8bf453 arm: stm32mp: add defconfig for trusted boot with FIP
Add TF-A FIP support for trusted boot on STM32MP15x,
when STM32MP15x_STM32IMAGE is not activated.

With FIP support the SSBL partition is named "fip" and its size is 4MB,
so the ENV partition name in device tree  (for SD card or eMMC)
or offset in defconfig (CONFIG_ENV_OFFSET / CONFIG_ENV_OFFSET_REDUND)
need to be modified.

With FIP the TEE MTD partitions are removed because the OP-TEE binray are
included in the FIP containers.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-16 09:36:31 +02:00
Patrick Delaunay
6de57b41dd arm: stm32mp: add config for STM32IMAGE support
By default for trusted boot with TF-A, U-Boot (u-boot-nodtb)
is located in FIP container with its device tree and with
the secure monitor (provided by TF-A or OP-TEE).
The FIP file is loaded by TF-A BL2 and each components is
extracted at the final location.

This patch add CONFIG_STM32MP15x_STM32IMAGE to request the
STM32 image generation for SOC STM32MP15x
when FIP container is not used (u-boot.stm32 is loaded by TF-A
as done previously to keep the backward compatibility).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-08-16 09:34:27 +02:00
Tom Rini
85ccbf666e Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Enable SeaBIOS support for Crown Bay
- Update SeaBIOS build instructions in the x86 doc
- Enable CONFIG_SPI_FLASH_SMART_HWCAPS for Crown Bay
2021-08-13 08:37:47 -04:00
Bin Meng
cedd754484 x86: crownbay: Enable CONFIG_SPI_FLASH_SMART_HWCAPS
Now that the spi-nor fix has been made in u-boot/master via:

  commit 87e7219f9c ("mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()")

enable CONFIG_SPI_FLASH_SMART_HWCAPS on Intel Crown Bay again.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-13 08:53:49 +08:00