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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

Browse source 
fsl-qoriq: Fixes related to env, spi, usb, crypto, configs, distro-boot
for Layerscape Boards like lx2, sl28, ls2088ardb.
powerpc: Fixes for t208xrdb revd board and cortina related configs
update for T208xRDB, T4240RDB.
This commit is contained in:
Tom Rini 2021-08-23 09:17:32 -04:00
commit 18f4e85876
41 changed files with 237 additions and 103 deletions
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6
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View file

@ -58,6 +58,7 @@ config ARCH_LS1043A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
select HAS_FSL_XHCI_USB if USB_HOST
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -89,6 +90,7 @@ config ARCH_LS1046A
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH2
select HAS_FSL_XHCI_USB if USB_HOST
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -245,6 +247,7 @@ config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
@ -642,9 +645,8 @@ config SPL_LDSCRIPT
config HAS_FSL_XHCI_USB
bool
default y if ARCH_LS1043A || ARCH_LS1046A
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
pins, select it when the pins are assigned to USB.
config SYS_FSL_BOOTROM_BASE

9
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View file

@ -953,12 +953,15 @@ int board_late_init(void)
#endif
#ifdef CONFIG_TFABOOT
/*
* Set bootcmd and mcinitcmd if they don't exist in the environment.
* Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does
* not exists in env
*/
if (!env_get("bootcmd"))
if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) {
// Set bootcmd and mcinitcmd as per boot source
fsl_setenv_bootcmd();
if (!env_get("mcinitcmd"))
fsl_setenv_mcinitcmd();
env_set("fsl_bootcmd_mcinitcmd_set", "y");
}
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();

55
arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
View file

@ -72,61 +72,6 @@
/* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
partition@0 {
reg = <0x000000 0x010000>;
label = "rcw";
read-only;
};
partition@10000 {
reg = <0x010000 0x0f0000>;
label = "failsafe bootloader";
read-only;
};
partition@100000 {
reg = <0x100000 0x040000>;
label = "failsafe DP firmware";
read-only;
};
partition@140000 {
reg = <0x140000 0x0a0000>;
label = "failsafe trusted firmware";
read-only;
};
partition@1e0000 {
reg = <0x1e0000 0x020000>;
label = "reserved";
read-only;
};
partition@200000 {
reg = <0x200000 0x010000>;
label = "configuration store";
};
partition@210000 {
reg = <0x210000 0x0f0000>;
label = "bootloader";
};
partition@300000 {
reg = <0x300000 0x040000>;
label = "DP firmware";
};
partition@340000 {
reg = <0x340000 0x0a0000>;
label = "trusted firmware";
};
partition@3e0000 {
reg = <0x3e0000 0x020000>;
label = "bootloader environment";
};
};
};

36
board/freescale/common/fsl_validate.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -498,8 +499,11 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
return ret;
ret = algo->hash_init(algo, &ctx);
if (ret)
if (ret) {
if (ctx)
free(ctx);
return ret;
}
/* Update hash for ESBC key */
#ifdef CONFIG_KEY_REVOCATION
@ -518,8 +522,11 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
/* Copy hash at destination buffer */
ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
if (ret)
if (ret) {
if (ctx)
free(ctx);
return ret;
}
for (i = 0; i < SHA256_BYTES; i++)
img->img_key_hash[i] = hash_val[i];
@ -547,14 +554,18 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
ret = algo->hash_init(algo, &ctx);
/* Copy hash at destination buffer */
if (ret)
if (ret) {
free(ctx);
return ret;
}
/* Update hash for CSF Header */
ret = algo->hash_update(algo, ctx,
(u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0);
if (ret)
if (ret) {
free(ctx);
return ret;
}
/* Update the hash with that of srk table if srk flag is 1
* If IE Table is selected, key is not added in the hash
@ -581,22 +592,29 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
key_hash = 1;
}
#endif
if (ret)
if (ret) {
free(ctx);
return ret;
if (!key_hash)
}
if (!key_hash) {
free(ctx);
return ERROR_KEY_TABLE_NOT_FOUND;
}
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
(u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
if (ret)
if (ret) {
free(ctx);
return ret;
}
/* Copy hash at destination buffer */
ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
if (ret)
if (ret) {
free(ctx);
return ret;
}
return 0;
}

38
board/freescale/ls2080ardb/ls2080ardb.c
View file

@ -33,6 +33,9 @@
#endif
#include "../common/vid.h"
#define CORTINA_FW_ADDR_IFCNOR 0x580980000
#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0x584980000
#define CORTINA_FW_ADDR_QSPI 0x980000
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
@ -235,6 +238,41 @@ int config_board_mux(int ctrl_type)
return 0;
}
ulong *cs4340_get_fw_addr(void)
{
#ifdef CONFIG_TFABOOT
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
#endif
ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
#ifdef CONFIG_TFABOOT
/* LS2088A TFA boot */
if (SVR_SOC_VER(svr) == SVR_LS2088A) {
enum boot_src src = get_boot_src();
u8 sw;
switch (src) {
case BOOT_SOURCE_IFC_NOR:
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & 0x0f);
if (sw == 0)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
else if (sw == 4)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
break;
case BOOT_SOURCE_QSPI_NOR:
/* Only one bank in QSPI */
cortina_fw_addr = CORTINA_FW_ADDR_QSPI;
break;
default:
printf("WARNING: Boot source not found\n");
}
}
#endif
return (ulong *)cortina_fw_addr;
}
int board_init(void)
{
#ifdef CONFIG_FSL_MC_ENET

4
board/freescale/t208xrdb/cpld.h
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor
* Copyright 2021 NXP
*/
/*
@ -42,3 +43,6 @@ void cpld_write(unsigned int reg, u8 value);
/* RSTCON Register */
#define CPLD_RSTCON_EDC_RST 0x04
/* MISCCSR Register */
#define CPLD_MISC_POR_EN 0x30

27
board/freescale/t208xrdb/t208xrdb.c
View file

@ -128,6 +128,13 @@ int misc_init_r(void)
reg |= CPLD_RSTCON_EDC_RST;
CPLD_WRITE(reset_ctl, reg);
/* Enable POR for boards revisions D and up */
if (get_hw_revision() >= 'D') {
reg = CPLD_READ(misc_csr);
reg |= CPLD_MISC_POR_EN;
CPLD_WRITE(misc_csr, reg);
}
return 0;
}
@ -158,3 +165,23 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
ulong *cs4340_get_fw_addr(void)
{
ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
u8 reg;
reg = CPLD_READ(flash_csr);
if (!(reg & CPLD_BOOT_SEL)) {
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
if (reg == 0)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
else if (reg == 4)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
}
#endif
return (ulong *)cortina_fw_addr;
}

3
board/freescale/t208xrdb/t208xrdb.h
View file

@ -7,6 +7,9 @@
#ifndef __CORENET_DS_H__
#define __CORENET_DS_H__
#define CORTINA_FW_ADDR_IFCNOR 0xefe00000
#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
void fdt_fixup_board_fman_ethernet(void *blob);

19
board/freescale/t4rdb/t4240rdb.c
View file

@ -151,3 +151,22 @@ void board_detail(void)
break;
}
}
ulong *cs4340_get_fw_addr(void)
{
ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
u8 sw;
sw = CPLD_READ(vbank);
sw = sw & CPLD_BANK_SEL_MASK;
if (sw == 0)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
else if (sw == 4)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
#endif
return (ulong *)cortina_fw_addr;
}

3
board/freescale/t4rdb/t4rdb.h
View file

@ -11,6 +11,9 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CORTINA_FW_ADDR_IFCNOR 0xefe00000
#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);

1
configs/T2080RDB_NAND_defconfig
View file

@ -69,6 +69,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_NAND=y
CONFIG_CORTINA_FW_ADDR=0x200000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y

1
configs/T2080RDB_SDCARD_defconfig
View file

@ -66,6 +66,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_MMC=y
CONFIG_CORTINA_FW_ADDR=0x114000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y

1
configs/T2080RDB_SPIFLASH_defconfig
View file

@ -68,6 +68,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
CONFIG_CORTINA_FW_ADDR=0x120000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y

1
configs/T2080RDB_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0xEFE00000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y

1
configs/T2080RDB_revD_NAND_defconfig
View file

@ -70,6 +70,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_NAND=y
CONFIG_CORTINA_FW_ADDR=0x200000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y

1
configs/T2080RDB_revD_SDCARD_defconfig
View file

@ -67,6 +67,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_MMC=y
CONFIG_CORTINA_FW_ADDR=0x114000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y

1
configs/T2080RDB_revD_SPIFLASH_defconfig
View file

@ -69,6 +69,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
CONFIG_CORTINA_FW_ADDR=0x120000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y

1
configs/T2080RDB_revD_defconfig
View file

@ -54,6 +54,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0xEFE00000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y

1
configs/T4240RDB_SDCARD_defconfig
View file

@ -57,6 +57,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x77f000
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y

1
configs/T4240RDB_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0xefe00000
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y

1
configs/ls2080ardb_SECURE_BOOT_defconfig
View file

@ -47,6 +47,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x580980000
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y

1
configs/ls2080ardb_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x580980000
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y

1
configs/ls2080ardb_nand_defconfig
View file

@ -58,6 +58,7 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y

1
configs/ls2081ardb_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_NVME=y

1
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

1
configs/ls2088ardb_qspi_defconfig
View file

@ -51,6 +51,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x980000
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y

1
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
View file

@ -51,6 +51,7 @@ CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y

1
configs/lx2160aqds_tfa_defconfig
View file

@ -58,6 +58,7 @@ CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y

1
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
View file

@ -47,6 +47,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y

1
configs/lx2160ardb_tfa_defconfig
View file

@ -56,6 +56,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y

1
configs/lx2160ardb_tfa_stmm_defconfig
View file

@ -56,6 +56,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y

2
drivers/crypto/fsl/jobdesc.c
View file

@ -300,7 +300,7 @@ void inline_cnstr_jobdesc_rng_deinstantiation(u32 *desc, int handle)
void inline_cnstr_jobdesc_rng(u32 *desc, void *data_out, u32 size)
{
dma_addr_t dma_data_out = virt_to_phys(data_out);
caam_dma_addr_t dma_data_out = virt_to_phys(data_out);
init_job_desc(desc, 0);
append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG |

10
drivers/net/phy/Kconfig
View file

@ -131,6 +131,16 @@ config SYS_CORTINA_FW_IN_SPIFLASH
endchoice
config CORTINA_FW_ADDR
hex "Cortina Firmware Address"
depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
default 0x0
config CORTINA_FW_LENGTH
hex "Cortina Firmware Length"
depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
default 0x40000
config PHY_CORTINA_ACCESS
bool "Cortina Access Ethernet PHYs support"
default y

79
drivers/net/phy/cortina.c
View file

@ -17,12 +17,11 @@
#include <linux/err.h>
#include <phy.h>
#include <cortina.h>
#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
#include <nand.h>
#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
#include <spi_flash.h>
#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
#include <mmc.h>
#ifdef CONFIG_ARM64
#include <asm/arch/cpu.h>
#endif
#ifndef CONFIG_PHYLIB_10G
@ -124,6 +123,11 @@ struct cortina_reg_config cortina_reg_cfg[] = {
{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
};
__weak ulong *cs4340_get_fw_addr(void)
{
return (ulong *)CONFIG_CORTINA_FW_ADDR;
}
void cs4340_upload_firmware(struct phy_device *phydev)
{
char line_temp[0x50] = {0};
@ -132,22 +136,76 @@ void cs4340_upload_firmware(struct phy_device *phydev)
int i, line_cnt = 0, column_cnt = 0;
struct cortina_reg_config fw_temp;
char *addr = NULL;
ulong cortina_fw_addr = (ulong)cs4340_get_fw_addr();
#ifdef CONFIG_TFABOOT
enum boot_src src = get_boot_src();
if (src == BOOT_SOURCE_IFC_NOR) {
addr = (char *)cortina_fw_addr;
} else if (src == BOOT_SOURCE_IFC_NAND) {
int ret;
size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
ret = nand_read(get_nand_dev_by_index(0),
(loff_t)cortina_fw_addr, &fw_length, (u_char *)addr);
if (ret == -EUCLEAN) {
printf("NAND read of Cortina firmware at 0x%lx failed %d\n",
cortina_fw_addr, ret);
}
} else if (src == BOOT_SOURCE_QSPI_NOR) {
int ret;
struct spi_flash *ucode_flash;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!ucode_flash) {
puts("SF: probe for Cortina ucode failed\n");
} else {
ret = spi_flash_read(ucode_flash, cortina_fw_addr,
CONFIG_CORTINA_FW_LENGTH, addr);
if (ret)
puts("SF: read for Cortina ucode failed\n");
spi_flash_free(ucode_flash);
}
} else if (src == BOOT_SOURCE_SD_MMC) {
int dev = CONFIG_SYS_MMC_ENV_DEV;
u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
u32 blk = cortina_fw_addr / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc) {
puts("Failed to find MMC device for Cortina ucode\n");
} else {
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
printf("MMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
#ifdef CONFIG_BLK
(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
#else
(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr);
#endif
}
}
#else /* CONFIG_TFABOOT */
#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
addr = (char *)CONFIG_CORTINA_FW_ADDR;
addr = (char *)cortina_fw_addr;
#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
int ret;
size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
ret = nand_read(get_nand_dev_by_index(0),
(loff_t)CONFIG_CORTINA_FW_ADDR,
(loff_t)cortina_fw_addr,
&fw_length, (u_char *)addr);
if (ret == -EUCLEAN) {
printf("NAND read of Cortina firmware at 0x%x failed %d\n",
CONFIG_CORTINA_FW_ADDR, ret);
printf("NAND read of Cortina firmware at 0x%lx failed %d\n",
cortina_fw_addr, ret);
}
#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
int ret;
@ -159,7 +217,7 @@ void cs4340_upload_firmware(struct phy_device *phydev)
if (!ucode_flash) {
puts("SF: probe for Cortina ucode failed\n");
} else {
ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
ret = spi_flash_read(ucode_flash, cortina_fw_addr,
CONFIG_CORTINA_FW_LENGTH, addr);
if (ret)
puts("SF: read for Cortina ucode failed\n");
@ -168,7 +226,7 @@ void cs4340_upload_firmware(struct phy_device *phydev)
#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
int dev = CONFIG_SYS_MMC_ENV_DEV;
u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
u32 blk = cortina_fw_addr / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc) {
@ -186,6 +244,7 @@ void cs4340_upload_firmware(struct phy_device *phydev)
addr);
#endif
}
#endif
#endif
while (*addr != 'Q') {
@ -195,7 +254,7 @@ void cs4340_upload_firmware(struct phy_device *phydev)
line_temp[i++] = *addr++;
if (0x50 < i) {
printf("Not found Cortina PHY ucode at 0x%p\n",
(char *)CONFIG_CORTINA_FW_ADDR);
(char *)cortina_fw_addr);
return;
}
}

2
drivers/spi/nxp_fspi.c
View file

@ -428,7 +428,7 @@ static bool nxp_fspi_supports_op(struct spi_slave *slave,
op->data.nbytes > f->devtype_data->txfifo)
return false;
return true;
return spi_mem_default_supports_op(slave, op);
}
/* Instead of busy looping invoke readl_poll_sleep_timeout functionality. */

2
env/Kconfig vendored
View file

@ -616,7 +616,7 @@ config SYS_RELOC_GD_ENV_ADDR
config SYS_MMC_ENV_DEV
int "mmc device number"
depends on ENV_IS_IN_MMC || ENV_IS_IN_FAT || SYS_LS_PPA_FW_IN_MMC || \
CMD_MVEBU_BUBT || FMAN_ENET || QE
CMD_MVEBU_BUBT || FMAN_ENET || QE || PHY_CORTINA
default 0
help
MMC device number on the platform where the environment is stored.

6
include/configs/T208xRDB.h
View file

@ -479,7 +479,6 @@ unsigned long get_board_ddr_clk(void);
* env, so we got 0x110000.
*/
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#define CONFIG_CORTINA_FW_ADDR 0x120000
#elif defined(CONFIG_SDCARD)
/*
@ -488,11 +487,9 @@ unsigned long get_board_ddr_clk(void);
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
#elif defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
@ -502,17 +499,14 @@ unsigned long get_board_ddr_clk(void);
* master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
#else
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
#define RGMII_PHY2_ADDR 0x02
#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */

2
include/configs/T4240RDB.h
View file

@ -517,8 +517,6 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_CORTINA_FW_ADDR 0xefe00000
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define SGMII_PHY_ADDR1 0x0
#define SGMII_PHY_ADDR2 0x1
#define SGMII_PHY_ADDR3 0x2

10
include/configs/ls2080ardb.h
View file

@ -560,14 +560,6 @@ unsigned long get_board_sys_clk(void);
#endif
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_CORTINA_FW_ADDR 0x20980000
#else
#define CONFIG_CORTINA_FW_ADDR 0x580980000
#endif
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define CORTINA_PHY_ADDR1 0x10
#define CORTINA_PHY_ADDR2 0x11
#define CORTINA_PHY_ADDR3 0x12
@ -577,9 +569,7 @@ unsigned long get_board_sys_clk(void);
#define AQ_PHY_ADDR3 0x02
#define AQ_PHY_ADDR4 0x03
#define AQR405_IRQ_MASK 0x36
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#endif
#include <asm/fsl_secure_boot.h>

4
include/configs/lx2160a_common.h
View file

@ -143,7 +143,6 @@
/* USB */
#ifdef CONFIG_USB_HOST
#define CONFIG_HAS_FSL_XHCI_USB
#ifndef CONFIG_TARGET_LX2162AQDS
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
@ -181,6 +180,7 @@ unsigned long get_board_ddr_clk(void);
#define XSPI_MC_INIT_CMD \
"sf probe 0:0 && " \
"sf read 0x80640000 0x640000 0x80000 && " \
"sf read $fdt_addr_r 0xf00000 0x100000 && " \
"env exists secureboot && " \
"esbc_validate 0x80640000 && " \
"esbc_validate 0x80680000; " \
@ -191,6 +191,7 @@ unsigned long get_board_ddr_clk(void);
#define SD_MC_INIT_CMD \
"mmc read 0x80a00000 0x5000 0x1200;" \
"mmc read 0x80e00000 0x7000 0x800;" \
"mmc read $fdt_addr_r 0x7800 0x800;" \
"env exists secureboot && " \
"mmc read 0x80640000 0x3200 0x20 && " \
"mmc read 0x80680000 0x3400 0x20 && " \
@ -201,6 +202,7 @@ unsigned long get_board_ddr_clk(void);
#define SD2_MC_INIT_CMD \
"mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
"mmc read 0x80e00000 0x7000 0x800;" \
"mmc read $fdt_addr_r 0x7800 0x800;" \
"env exists secureboot && " \
"mmc read 0x80640000 0x3200 0x20 && " \
"mmc read 0x80680000 0x3400 0x20 && " \

2
scripts/config_whitelist.txt
View file

@ -190,8 +190,6 @@ CONFIG_CONS_SCIF1
CONFIG_CONS_SCIF2
CONFIG_CONS_SCIF4
CONFIG_CON_ROT
CONFIG_CORTINA_FW_ADDR
CONFIG_CORTINA_FW_LENGTH
CONFIG_CPLD_BR_PRELIM
CONFIG_CPLD_OR_PRELIM
CONFIG_CPM2