pdnb3 and scpu are explicitly on LIST_ixp, even though they are
also specified in boards.cfg as having cpu ixp. This means that
they will be built twice when doing ./MAKEALL ixp, or ./MAKEALL arm.
This was pointless before, but actually breaks things if you launch
both builds at the same time, as they overwrite each other.
Signed-off-by: Andy Fleming <afleming@freescale.com>
All arches init this the same way, so move the logic into the core
net code to avoid duplicating it everywhere else.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
This field gets read in one place (by "bdinfo"), and we can replace
that with getenv("ipaddr"). After all, the bi_ip_addr field is kept
up-to-date implicitly with the value of the ipaddr env var.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
As originally reported against beagleboard we currently have the
following error message reported in SPL:
U-Boot SPL 2012.04-00020-gb8310b9-dirty (Apr 25 2012 - 18:49:57)
Texas Instruments Revision detection unimplemented
OMAP SD/MMC: 0
timed out in wait_for_bb: I2C_STAT=1000
reading u-boot.img
....
The reason for above message is that when booting from MMC, I2C needs to
be initialized to talk with the TWL4030. On OMAP3 I2C is only
initalized in SPL if CONFIG_SPL_BOARD_INIT is set.
Cc: Thomas Weber <weber@corscience.de>
Cc: Steve Sakoman <sakoman@gmail.com>
Original patch for Beagleboard is:
Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
Extended to cover all other boards:
Signed-off-by: Tom Rini <trini@ti.com>
With older toolchains it is possible to not fit entirely into the 45KB
that we had assigned to SPL. Adjust to allow for 8KB of stack (which
should be more than required) and 54KB of text/data.
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Vaibhav Hiremath <hvaibhav@ti.com>
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code
incorrectly sets the DPLL4 clock input divider to /6.5 which
is an invalid value unless the input clock is 13MHz. When a JTAG
emulator is attached, a warm reset is necessary after the emulator
gains control of the process. This results in a loss of serial
output due to the invalid DPLL4 settings.
This patch fixes the issue by resetting the DPLL4 clock input
divider to /1 when the input clock is not 13MHz. AM/DM37x TRM
section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only
used when the input clock is 13MHz.
Signed-off-by: Matt Porter <mporter@ti.com>
For OMAP4 boards, such as the panda-es, that have 1GB of memory the linux
kernel fails to locate the device tree blob on boot. The reason being is that
u-boot is copying the DT blob to the upper part of RAM when booting the kernel
and the kernel is unable to access the blob. By setting the fdt_high variable
to either 0xffffffff (to prevent the copy) or 0xac000000 (704MB boundary
of memory for OMAP4) the kernel is able to locate the DT blob and boot.
Based upon following patch by Dirk Behme set the fdt_high variable to allow
booting with device tree on OMAP4 boards.
"7e9603e i.mx6q: configs: Add fdt_high and initrd_high variables"
Cc: Sricharan R <r.sricharan@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Booting up these cores (dsp / ivahd / cortex-m3) is bad without
firmware running on them, and they will hang preventing any kind
of sleep transitions later on with the kernel.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: R Sricharan <r.sricharan@ti.com>
If this is done in the bootloader, the FS-USB will later be stuck into
intransition state, which will prevent the device from entering idle.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
If uart2 is enabled during boot, spurious wifi chip transmission will
hang the module and it is impossible to recover from this situation
without hard reset. This will prevent any l4_per domain idle
transitions.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
This patch changes the default mpurate variable from 500 to auto on
all IGEP boards, with this the default rate is autoselected.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Based on commit cf073e49bc for beagleboard
Using the new env import command it is possible to use plain text files instead
of script-images. Plain text files are much easier to handle.
E.g. If your boot.scr contains the following:
-----------------------------------
setenv dvimode 1024x768-16@60
run loaduimage
run mmcboot
-----------------------------------
you could create a file named uEnv.txt and use that instead of boot.scr:
-----------------------------------
dvimode=1024x768-16@60
uenvcmd=run loaduimage; run mmcboot
-----------------------------------
The variable uenvcmd (if existent) will be executed (using run) after uEnv.txt
was loaded. If uenvcmd doesn't exist the default boot sequence will be started,
therefore you could just use
-----------------------------------
dvimode=1024x768-16@60
-----------------------------------
as uEnv.txt because loaduimage and mmcboot is part of the default boot sequence
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This is needed for upcoming Toradex Colibri T20 upstream support.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for internal matrix keyboard controller for Nvidia Tegra
platforms. This driver uses the fdt decode function to obtain its key
codes.
Support for the Ctrl modifier is provided. The left and right ctrl keys are
dealt with in the same way.
This uses the new keyboard input library (drivers/input/input.c) to decode
keys and handle most of the common input logic. The new key matrix library
is also used to decode (row, column) key positions into key codes.
The intent is to make this driver purely about dealing with the hardware.
Key detection before the driver is loaded is supported. This key will be
picked up when the keyboard driver is initialized.
Modified by Bernie Thompson <bhthompson@chromium.org> and
Simon Glass <sjg@chromium.org> for device tree, input layer, key matrix
and various other things.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Seaboard uses a QUERTY keyboard. We add key codes for this to
enable key scanning to work.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra keyboard controller provides a simple interface to a matrix
keyboard.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Matrix keyboards require a key map to be set up, and must also deal with
key ghosting.
Create a keyboard matrix management implementation which can be leveraged
by various keyboard drivers. This includes code to read the keymap from
the FDT and perform debouncing.
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a module which understands converting key codes (or scan codes)
to ASCII characters. It includes FIFO support and can call back to
drivers to read new characters when its FIFO is empty.
Keycode maps are provided for un-modified, shift and ctrl keys.
The plan is to use this module where such mapping is required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to able to decode Linux fdt keymaps, so bring part of this
enormous header file over to U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Sometimes we don't need a full cell for each value. This provides
a simple function to read a byte array, both with and without
copying it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds timings for T20 and T25 Seaboards, using the bindings found here:
http://patchwork.ozlabs.org/patch/132928/
We supply both full speed options for normal running, and half speed options
for testing / development.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add tegra_i2c_get_dvc_bus_num() to obtain the I2C bus number of DVC bus.
This allows us to talk to the PMU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a definition of the memory controller node according to the bindings
here:
http://patchwork.ozlabs.org/patch/132928/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Set Seaboard to optimal memory settings based on the SOC in use (T20 or T25).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra core power rail has leakage voltage around 0.2V while system in
suspend mode. The source of the leakage should be coming from PMC power
detect logic for IO rails power detection.
That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0'
to PWR_DET (APBDEV_PMC_PWR_DET_0).
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Call the function to put warmboot boot in a suitable place for resume.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Save SDRAM parameters into the warmboot scratch registers
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add code to set up the warm boot area in the Tegra CPU ready for a
resume after suspend.
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Power supplies must be adjusted in line with clock frequency. This code
provides a simple routine to set the voltage to allow operation at maximum
frequency.
- Split PMU code into separate TPS6586X driver
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add support for setting up the memory controller parameters. Boards
can set up an appropriate table in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a basic header file for this register, to be filled in as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to know which type of chip we are running on - the Tegra
family has several SKUs. This can be determined by reading a
fuse register, so add this function to ap20.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These headers provide access to additional Tegra features.
flow - start/stop CPUs
sdram - parameters for SDRAM
fuse - access to on-chip fuses / security settings
gp_padctl - pad control and general purpose registers
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Provides an interface to aes.c for the warmboot code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
