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ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
With older toolchains it is possible to not fit entirely into the 45KB that we had assigned to SPL. Adjust to allow for 8KB of stack (which should be more than required) and 54KB of text/data. Cc: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Thomas Weber <weber@corscience.de> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Vaibhav Hiremath <hvaibhav@ti.com>
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parent
a3c3fabb0f
commit
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10 changed files with 11 additions and 11 deletions
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@ -34,14 +34,14 @@ DDR1: 0x80000000 - 0xBFFFFFFF
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Option 1 (SPL only):
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0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
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0x4020BC00 - 0x4020FFFC: Area for the SPL stack.
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0x4020E000 - 0x4020FFFC: Area for the SPL stack.
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0x80000000 - 0x8007FFFF: Area for the SPL BSS.
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0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot
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0x80208000 - 0x80307FFF: malloc() pool available to SPL.
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Option 2 (SPL or X-Loader):
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0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
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0x4020BC00 - 0x4020FFFC: Area for the SPL stack.
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0x4020E000 - 0x4020FFFC: Area for the SPL stack.
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0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot
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0x87000000 - 0x8707FFFF: Area for the SPL BSS.
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0x87080000 - 0x870FFFFF: malloc() pool available to SPL.
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@ -325,7 +325,7 @@
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#define CONFIG_SPL
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (45 * 1024)
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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@ -324,7 +324,7 @@
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#define CONFIG_SPL
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (45 * 1024)
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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@ -324,7 +324,7 @@
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
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@ -325,7 +325,7 @@
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE (45 << 10)
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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/* move malloc and bss high to prevent clashing with the main image */
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@ -399,7 +399,7 @@
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#define CONFIG_SPL
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (45 * 1024)
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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@ -282,7 +282,7 @@
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/* Defines for SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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@ -303,7 +303,7 @@
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#define CONFIG_SPL
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (45 * 1024)
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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/* move malloc and bss high to prevent clashing with the main image */
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@ -257,7 +257,7 @@
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE (45 << 10) /* 45 K */
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
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@ -293,7 +293,7 @@
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
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