The current eficonfig menu does not support vertical scroll,
so it can not display the menu entries greater than
the console row size.
This commit add the vertial scroll support.
The console size is retrieved by
SIMPLE_TEXT_OUTPUT_PROTOCOL.QueryMode() service, then
calculates the row size for menu entry by subtracting
menu header and description row size from the console row size.
"start" and "end" are added in the efimenu structure.
"start" keeps the menu entry index at the top, "end" keeps
the bottom menu entry index. item_data_print() menu function
only draws the menu entry between "start" and "end".
This commit also fixes the issue that "Save" and "Quit"
entries can be moved by BKEY_PLUS in change boot order menu.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
This commit removes the change boot order specific
menu implementation. The change boot order implementation
calls eficonfig_process_common() same as other menus.
The change boot order menu requires own item_data_print
and item_choice implementation, but display_statusline
function can be a same function as other menus.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Current change boot order implementation does not call
eficonfig_process_common() and call own menu functions
for display_statusline, item_data_print and item_choice.
Change boot order functionality should call
eficonfig_process_common() to improve maintenanceability.
This commit is a preparation to remove the change boot
order specific implementation. The menu functions
(display_statusline, item_data_print and item_choice) are
added as argument of eficonfig_process_common().
The menu description string displayed at the bottom of
the menu is also added as argument.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
There is no variable num_pages in function efi_esrt_allocate_install().
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
This section does not match the standards of our documentation.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move section 'Directory hierarchy' from file README to the HTML
documentation.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The information is already maintained in doc/develop/release_cycle.rst.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move the README section to the HTML documentation.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Board configurations are in configs/ and not in the Makefile.
git log is the adequate way to identify who contributed to our source.
scripts/get_maintainer.pl is the correct way to identify maintainers.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The information in this section is outdated.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove description of coding standards and patch submission process.
Link to the relevant HTML documentation instead.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
sandbox.rst was moved.
Fixes: 2851cc94f3 ("dm: Add documentation for host command and implementation")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use internal rst reference with :doc: to have a link to distro.rst page
in the generated U-Boot documentation.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* Indicate the location of the directory for EFI capsules.
* Improve the readability.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* add return values
* move configuration to separate section to match other man-pages
* fix typo
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The actual function being documented is jump_to_image_optee(), not
jump_to_image_linux().
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Provide a man-page for the sleep command.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The 'Example' heading should be on a lower level than 'bdinfo command'.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the CROSS_COMPILE flag as we assume we build in a cross environment.
Also improve the comment about copying the binary to SD card.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
This adds a guide for copying the raw bootloader image on the SD card
to the SPI NOR using U-Boot itself.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Use the latest version of the NXP TF-A code and add a note about
quirks with GCC 12.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Convert Note: to ..note::
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* Use 16 digits on 64 bit systems.
* Use 64 bit patterns on 64 bit systems.
* Expect the sign bit in bit 63 on 64 bit systems.
* Adjust the formatting of a constant.
* Always print result on new line
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Binman positioning by ELF symbol
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Merge tag 'dm-pull-26jan23' of https://source.denx.de/u-boot/custodians/u-boot-dm
FIT improvements with split-elf, especially for Rockchip
Binman positioning by ELF symbol
Unfortunately a recent patch snuck through without the require test
coverage. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 571bc4e67d ("binman: Support positioning an entry by and ELF symbol")
Use a more accurate check for determining if the full format string will
be handled correctly, since SPL_USE_TINY_PRINTF can be disabled.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This property sets the minimum size of an entry, including padding but
not alignment. It can be used to reserve space for growth of an entry,
or to enforce a minimum offset for later entries in the section.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The FIT generated after the switch to using binman is using different
values for firmware and loadables properties compared to the old script.
With the old script:
firmware = "atf-1";
loadables = "u-boot", "atf-2", ...;
After switch to binman:
firmware = "u-boot";
loadables = "atf-1", "atf-2", ...;
This change result in SPL jumping directly into U-Boot proper instead of
initializing TF-A.
With this patch the properties change back to:
firmware = "atf-1";
loatables = "u-boot", "atf-2", ...;
Fixes: e0c0efff2a ("rockchip: Support building the all output files in binman")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
In some cases it is desired for SPL to start TF-A instead of U-Boot
proper. Add support for a new property fit,firmware that picks a
valid entry and prepends the remaining valid entries to the
loadables list generated by the split-elf generator.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add sha256 hash to FIT images when CONFIG_SPL_FIT_SIGNATURE=y.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Special nodes, hash and signature, is not being added to the nodes
generated for each segment in split-elf operation.
Copy the subnode logic used in _gen_fdt_nodes to _gen_split_elf to
ensure special nodes are added to the generated nodes.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
SPL load FIT images by reading the data aligned to block length.
Block length aligned image data is read directly to the load address.
Unaligned image data is written to an offset of the load address and
then the data is memcpy to the load address.
This adds a small overhead of having to memcpy unaligned data, something
that normally is not an issue.
However, TF-A may have a segment that should be loaded into SRAM, e.g.
vendor TF-A for RK3568 has a 8KiB segment that should be loaded into the
8KiB PMU SRAM. Having the image data for such segment unaligned result
in segment being written to and memcpy from beyond the SRAM boundary, in
the end this results in invalid data in SRAM.
Aligning the FIT and its external data to MMC block length to work
around such issue.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support to indicate what alignment to use for the FIT and its
external data. Pass the alignment to mkimage via the -B flag.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and
differences comparing to other Spansion/Cypress flash familes are:
- 4-byte address mode by factory default
- Quad mode is enabled by factory default
- Supports mixture of 128KB and 64KB sectors by OTP configuration
(this patch supports uniform 128KB only)
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Rename s25hx_t prefix to s25 so that the single set of fixup hooks can
support all other S25 families.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Acked-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
If the offset or the size passed to the 'sf erase' command exceeds
the size of the SPI flash displaying the command usage is not
helpful. Return CMD_RET_FAILURE instead of CMD_RET_USAGE.
Use the CMD_RET_* constants instead of 0, 1, -1.
Simplify a logical expression in the final return statement.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
CMD_RET_USAGE == -1. The special handling of this value at the end of
do_spi_flash() does not make any sense.
To avoid future confusion use the CMD_RET_* constants and simplify the
code.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
If the offset or the size passed to the 'sf write' or 'sf read' command
exceeds the size of the SPI flash displaying the command usage is not
helpful. Return CMD_RET_FAILURE instead of CMD_RET_USAGE.
Use the CMD_RET_* constants instead of 0, 1, -1.
Simplify a logical expression in the final return statement.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Fix the issue where some flash chips like cypress S25HS256T return the
value of the same register over and over in DAC mode.
For example in the TI K3-AM62x Processors refer [0] Technical Reference
Manual there is a layer of digital logic in front of the QSPI/OSPI
Drive when used in DAC mode. This is part of the Flash Subsystem (FSS)
which provides access to external Flash devices.
The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for
OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit
mode enabled by default.
Thus, by default controller operates in 32 bit mode causing it to always
align all data to 4 bytes from a 4byte aligned address. In some flash
chips like cypress for example if we try to read some regs in DAC mode
then it keeps sending the value of the first register that was requested
and inorder to read the next reg, we have to stop and re-initiate a new
transaction.
This causes wrong register values to be read than what is desired when
registers are read in DAC mode. Hence if the data.nbytes is very less
then prefer STIG mode for such small reads.
[0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
[jagan: add tab space for comments]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Setup the Addr bit field while issuing register reads in STIG mode. This
is needed for example flashes like cypress define in their transaction
table that to read any register there is 1 cmd byte and a few more address
bytes trailing the cmd byte. Absence of addr bytes will obviously fail
to read correct data from flash register that maybe requested by flash
driver because the controller doesn't even specify which address of the
flash register the read is being requested from.
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cypress defines two flavors of configuration registers, volatile and
non volatile, and both use the same bit fields. Rename the bitfields in
the configuration registers so that they can be used for both flavors.
Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
CFR5[6] is reserved bit and must be always 1. Set it to comply with flash
requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition,
stop using magic numbers and describe the missing bit fields in CFR5
register. This is useful for both readability and future possible addition
of Octal STR mode support.
Fixes: ea9a22f7e7 ("mtd: spi-nor-core: Add support for Cypress Semper flash")
Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Introduce Socionext F_OSPI controller driver. This controller is used to
communicate with slave devices such as SPI flash memories. It supports
4 slave devices and up to 8-bit wide bus, but supports master mode only.
This driver uses spi-mem framework for SPI flash memory access, and
can only operate indirect access mode and single data rate mode.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Use log_warning() instead of printf() to print out driver information
Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
