Commit 56c2dbdaba ("imx: bootaux: cleanup code") introduces the
following LTO related warning:
"
arch/arm/mach-imx/imx_bootaux.c:24:31: warning: type of ‘hostmap’ does not match original declaration [-Wlto-type-mismatch]
24 | const __weak struct rproc_att hostmap[] = { };
| ^
arch/arm/mach-imx/imx8m/soc.c:1590:24: note: array types have different bounds
1590 | const struct rproc_att hostmap[] = {
| ^
arch/arm/mach-imx/imx8m/soc.c:1590:24: note: ‘hostmap’ was previously declared here
../aarch64-linux-gnu/bin/ld: warning: u-boot has a LOAD segment with RWX permissions
"
This is because the weak empty array of structures "hostmap" is eventually
replaced by non-empty array of structures with different number of elements.
Fix this by avoiding weak variable size array, instead use a weak function
which returns single pointer to the array.
Fixes: 56c2dbdaba ("imx: bootaux: cleanup code")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function
prototype common and usable by i.MX9.
Also include mmc env functions that use ROM API.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
For SoCs support ROM API, CONFIG_SPL_BOOTROM_SUPPORT is needed,
so use this macro to guard the code to avoid extend the list.
And drop the guard with structure definition, there is no need.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The ROM API is thoroughly undocumented, but apparently passing the xor
of the real arguments as an extra argument is required [1]. Also, we
need to do the "save gd/restore gd" dance. These are both error-prone,
and lead to a lot of code duplication.
Since both imx8m[np] and imx8ulp SOCs have this, add a separate
translation unit which is included precisely when the new
CONFIG_IMX8_ROMAPI symbol is set, which provide convenience wrappers
that take care of computing the xor value as well as doing the gd
dance, and that thus have a more intuitive API. Subsequent patches
will make use of these to reduce boilerplate.
[1] One wonders, for example, if the check is only applied to the
lower 32 bits, or if we're implicitly relying on all 64-bit pointer
values we're passing effectively have 0 in the upper 32 bits.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
This exposes the struct rom_api, the g_rom_api variable declaration
and the associated #defines to slightly fewer boards: namely, those
IMX8M which are not IMX8MN or IMX8MP. But the latter two are the only
IMX8M* ones where the g_rom_api variable is defined (in imx8m/soc.c),
so that should be fine.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Decode ECSPI boot device in env_get_location() from i.MX8M ROMAPI tables.
This is necessary to correctly identify env is in SPI NOR when the system
boots from SPI NOR attached to ECSPI.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The interface for NOR/OneNAND is called "EIM" not "EMI". Fix this.
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Similar to what has been done before with c5437e5b for u-boot proper, we
enable the SMP bit for SPL as well. This is necessary when SDP booting
straight into Linux, i.e. falcon boot. When SDP boot mode is active, the
ROM code does not set this bit which makes the caches not work once
activated in Linux.
On an i.MX6ULL (528MHz), this reduces a minimal kernel's boot time into
an initramfs shell from ~6.1s down to ~1.2s.
Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
i.MX8ULP support using ROM API to load container image,
it use same ROM API as i.MX8MN/MP, and use same container format
as i.MX8QM/QXP.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We need those macros to instruct drivers on how to behave for SoC specific
quirks, so let's add it as done for other i.MX SoCs.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
There are 3 part numbers for 11x11 i.MX8MNano with different core number
configuration: UltraLite Quad/Dual/Solo
Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So
checking the MIPI DSI disable fuse to recognize these parts.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Introduce weak function board_mem_get_layout() which allows overriding
the memory layout from board code in runtime, useful for handling
different SKU versions.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so
update u-boot to remove decoding and support for those parts.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The i.MX6/i.MX7 is capable of booting a secondary "redundant" system
image in case the primary one is corrupted. The user can force this
boot mode as well by explicitly setting SRC GPR10 bit 30. This can be
potentially useful when upgrading the bootloader itself. Expose this
functionality to the user.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Add the basic differentiation between i.MX6 and i.MX7 into the bmode
command, the mechanism really works almost the same on both platforms.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
iMX8MP has 6 fused parts in each qualification tier, with core, VPU,
ISP, NPU or DSP fused respectively.
The configuration tables for enabled modules:
MIMX8ML8DVNLZAA Quad Core, VPU, NPU, ISP, DSP
MIMX8ML7DVNLZAA Quad Core, NPU, ISP
MIMX8ML6DVNLZAA Quad Core, VPU, ISP
MIMX8ML5DVNLZAA Quad Core, VPU
MIMX8ML4DVNLZAA Quad Lite
MIMX8ML3DVNLZAA Dual Core, VPU, NPU, ISP, DSP
Add the support in U-Boot
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
It is bad practice to include common.h in other header files since it can
bring in any number of superfluous definitions. It implies that some C
files don't include it and thus may be missing CONFIG options that are set
up by that file. The C files should include these themselves.
Update some header files in arch/arm to drop this.
Signed-off-by: Simon Glass <sjg@chromium.org>
imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
There are different parts from one SoC. Take i.MX6ULL for example,
some part might not have ENET, some might have; some might not have
USB, some might have. The information could be got from OCOTP,
to make one image support the different parts, we need runtime
disable linux kernel dts node and uboot driver probe if the
corresponding module not exists in the part.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could
share same macro, then we no need to add is_imx6ulz in various drivers.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MP use 0x182 as its ID, so 0xff is not valid to get the cpu type,
extend it to 0x1ff.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Currently imx-specific bootaux command doesn't support ELF format
firmware for Cortex-M4 core.
This patches introduces a PoC implementation of handling elf firmware
(load_elf_image_phdr() was copy-pasted from elf.c just for PoC).
ELF64 binaries isn't supported yet.
This has the advantage that the user does not need to know to which
address the binary has been linked to. However, in order to handle
and load the elf sections to the right address, we need to translate the
Cortex-M4 core memory addresses to primary/host CPU memory
addresses (Cortex A7/A9 cores).
This allows to boot firmwares from any location with just using
bootaux, e.g.:
> tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr}
Similar translation table can be found in the Linux remoteproc
driver [1].
[1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for
the rpmsg communication. Both use cases need a fixed location of
memory reserved. For the rpmsg use case the reserved area needs
to be in sync with the kernel's hardcoded vring descriptor location.
Use the linux,usable-memory property to carve out 1MB of memory
in case the M4 core is running. Also make sure that the i.MX 7
specific rpmsg driver does not get loaded in case we do not carve
out memory.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
i.MX8MN support loading images with rom api, so we implement
reuse board_return_to_bootrom to let ROM loading images.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ,
so update the interface to add new argument.
Signed-off-by: Ye Li <ye.li@nxp.com>
[agust: fixed imx8m-power-domain build]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
imx6_is_bmode_from_gpr9 always returns false, because
IMX6_SRC_GPR10_BMODE is 1<<28 and gets casted to u8 on return.
This moves the function body into imx6_src_get_boot_mode, since that is the
only one using it and it is on the same abstraction level (accessing
registers directly).
Signed-off-by: Claudius Heine <ch@denx.de>
Add i.MX6ULZ cpu type and helper.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
According to "Table 5-1. Boot Device Select" (page 335,
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017)
the BOOT_CFG1[3] have following values (regarding EIM booting):
0 - NOR flash and 1 - ONENAND
This commit provides correct identification of the boot medium for IMX6Q
boards booting from NOR memory (MCCMON6 is one of them).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
Working with HAB on the i.MX7 we've encountered a case where a board that
successfully authenticates u-boot when booting Linux via OPTEE subsequently
fails to properly bring up the RTC.
The RTC registers live in the low-power block of the Secure Non-Volatile
Storage (SNVS) block.
The root cause of the error has been traced to the HAB handing off the
SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the
Non-Privileged Software Access Enable bit is zero. In ordinary
circumstances this is OK since we typically do not run in TZ mode, however
when we boot via HAB and enablng TrustZone, it is required to set
HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have
sufficient permissions to manipulate the SNVS-LP block.
On our reference board it is the difference between Linux doing this:
root@imx7s-warp-mbl:~# dmesg | grep rtc
snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034
snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038
snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000
snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004
snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered
30370000.snvs:snvs-rtc-lp as rtc0
snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864)
and doing this:
root@imx7s-warp-mbl:~# dmesg | grep rtc
snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034
snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038
snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000
snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004
snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110
snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110
hctosys: unable to open rtc device (rtc0)
Note bit 1 of LPCR is not set in the second case and is set in the first
case and that bit 31 of HPCOMR is set in the second case but not in the
first.
Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone
and continue onto the kernel. The kernel then has the necessary permissions
to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in
contrast - in the failing case the non-privileged kernel cannot do so.
This patch adds a simple init_snvs() call which sets the permission-bit
called from soc.c for the i.MX7. It may be possible, safe and desirable to
perform this on other i.MX processors but for now this is only tested on
i.MX7 as working.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Add SiP (Silicon Provider) services function to issue
SMC call to Arm Trusted Firmware.
More SiP information could be found in
https://github.com/ARM-software/arm-trusted-firmware/blob/master/
docs/arm-sip-service.rst
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
commit 20f1471416 ("imx: spl: Update NAND bootmode detection bit")
broke the NAND bootmode detection by checking if
BOOT_CFG1[7:4] == 0x8 for NAND boot mode.
This commit essentially reverts it, while using the IMX6_BMODE_*
macros that were introduced since.
Tables 8-7 & 8-10 from IMX6DQRM say the NAND boot mode selection
is done when BOOT_CFG1[7] is 1, but BOOT_CFG1[6:4] is not
necessarily 0x0 in this case.
Actually, NAND boot mode is when 0x8 <= BOOT_CFG1[7:4] <= 0xf,
like it was in the code before.
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tim Harvey <tharvey@gateworks.com>
