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2 commits

Author SHA1 Message Date
Hoegeun Kwon
422fc299df clk: starfive: pll: Fix to use postdiv1_mask 
There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.

Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
 2023-07-06 17:28:08 +08:00
Yanhong Wang
c13fe7c034 clk: starfive: Add StarFive JH7110 clock driver 
Add a DM clock driver for StarFive JH7110 SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
 2023-04-20 16:08:44 +08:00