Commit graph

17 commits

Author SHA1 Message Date
Simon Glass
a08afb398b x86: coreboot: Enable io command
Enable the io command for x86 on coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-26 10:36:25 -08:00
Simon Glass
ac426b7290 x86: Fix coreboot config to boot on Chromebook
The config is current broken. It compiles but does not boot because IDE is
enabled. Remove all IDE options, and enable SCSI instead.

Also add a working boot command and Linux bootargs, and enable command
line editing to make it easier to work with.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:45 -08:00
Gabe Black
d954a431ec x86: Turn on support for EFI's GPT in the coreboot config
This allows u-boot to figure out the partitions of a chrome-os install.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Simon Glass
cbca883c46 x86: coreboot: Enable video display
Enable the display on coreboot, using CFB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
300081aa68 x86: Emit port 80 post codes in show_boot_progress()
This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Simon Glass
34d6057be1 x86: Enable CONFIG_CMD_ZBOOT for coreboot
Enable this option to support booting a zImage.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Simon Glass
a7e6d5496c x86: Enable ICH6 GPIO controller for coreboot
Coreboot uses this controller to implement GPIO access.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Simon Glass
a78d49473c x86: Define CONFIG_SYS_VSNPRINTF for coreboot
This option protects the printf() functions from overflow.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Simon Glass
420a2ca73f x86: Select stdio devices for coreboot
We want to support VGA, serial, USB keyboard and the Coreboot memory
console buffer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:03 -08:00
Simon Glass
d02a568e9a x86: coreboot: Enable LPC TPM
Coreboot boards have an LPC TPM connected, so enable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:05 -08:00
Simon Glass
cd23e6923f x86: Remove coreboot start16 code
Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:05 -08:00
Graeme Russ
8d61625d6a x86: Put global data on the stack
Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Simon Glass
51bdad67cb x86: config: Enable AHCI support for coreboot
Enable AHCI driver for Intel SATA devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-02 15:20:43 -07:00
Simon Glass
af9f881a51 config: Enable CBFS, ext4 for coreboot
Enable Coreboot and EXT4 Filesystems on the coreboot board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-22 08:29:55 -07:00
Marek Vasut
bffe31c144 serial: Remove CONFIG_SERIAL_MULTI from config files
Remove any notion of CONFIG_SERIAL_MULTI from board config files.
Since CONFIG_SERIAL_MULTI is now enabled by default, it is useless
to specify this config option in the board config files. Therefore
remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-15 11:53:58 -07:00
Fabio Estevam
db917fbfed configs: Remove CONFIG_NET_MULTI from board files
CONFIG_NET_MULTI is not used anymore, so remove it from board files.

Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Kumar Gala <kumar.gala@freescale.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Heiko Schocher <hs@denx.de>
2012-02-12 10:11:26 +01:00
Gabe Black
ef5a5b0049 x86: Initial commit for running as a coreboot payload
Add a target for running u-boot as a coreboot payload in boards.cfg, a
board, CPU and a config. This is a skeleton implementation which always
reports the size of memory as 64 MB.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:15 +11:00