Commit graph

9 commits

Author SHA1 Message Date
Stefan Roese
86446d3a5d POST: Add disable interrupts in some of the missing CPU POST tests
Some CPU POST tests did not disable the interrupts while running. This
seems to be necessary to protect this self modifying code.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-20 23:00:22 +02:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Yuri Tikhonov
2d2b994a30 POST: move CONFIG_POST to Makefiles
Introduce the new logical option CONFIG_HAS_POST which is set when the
platform has CONFIG_POST set. Use CONFIG_HAS_POST in the post/ Makefiles
to determine should the POST libs be compiled for the selected target
platform, or not.

To avoid breaking u-boot linking process, the empty post/libpost.a file is
created for platforms which do not have POSTs.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-04-22 14:40:19 +02:00
Yuri Tikhonov
0a51e9248e POST: preparations for moving CONFIG_POST to Makefiles
Remove CONFIG_POST ifdefs from the post/ source files.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-04-22 14:38:38 +02:00
Yuri Tikhonov
928d1d77f8 Fix CPU POST test failure
The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the
ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered
by it. The gcc-4.2 with its more aggressive optimization exposes this fact.
This patch just saves the CR value before running the test code, so allowing
it to do anything it wants with CR.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Acked-by: Yuri Tikhonov <yur@emcraft.com>
--
2008-02-21 11:25:47 +01:00
Stefan Roese
3db93b8bed ppc4xx: Enable CPU POST test for 4xx with dcache enabled
Now with caches enabled (i- and d-cache) on 44x, we need a chance to
disable the cache for the CPU POST tests, since these tests consist
of self modifying code. This is done via the new change_tlb() function.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Sergei Poselenov
b44896215a Merged POST framework with the current TOT.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2007-07-05 08:17:37 +02:00
Igor Lisitsin
a11e06965e Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440.

Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
2007-06-22 23:21:01 +02:00
Wolfgang Denk
ad5bb451ad Restructure POST directory to support of other CPUs, boards, etc. 2007-03-06 18:08:43 +01:00