Commit graph

60110 commits

Author SHA1 Message Date
Suniel Mahesh
24e443978a arm: am437x: cm-t43: Enable DM for MMC, USB, SPI, SPI_FLASH, enable BLK
Enable driver model for USB, MMC, SPI and SPI_FLASH. Also enable BLK.
This will remove the following compile warnings:

===================== WARNING ======================
This board does not use CONFIG_DM_MMC. Please update
the board to use CONFIG_DM_MMC before the v2019.04 release.
====================================================
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
====================================================
===================== WARNING ======================
This board does not use CONFIG_DM_SPI_FLASH. Please update
the board to use CONFIG_SPI_FLASH before the v2019.07 release.
====================================================
Target was compile tested, build was clean.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-09-13 11:56:08 -04:00
Suniel Mahesh
d60eb8e49e arm: am437x: cm-t43: Add device tree, enable OF_CONTROL
Add device tree from Linux for driver model conversion
and enable OF_CONTROL. This will remove the following compile
warning:
==================================================
Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument
===================================================
Target was compile tested, build was clean.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-09-13 11:56:08 -04:00
Vignesh Raghavendra
62a9620135 soc: ti: k3-navss-ringacc: fix k3_nav_ringacc_ring_reset_dma
In case dma_ring_reset_quirk is not set the k3_ringacc_ring_reset_dma will
just exit without ring reset. Fix it, by adding ring reset call in case
dma_ring_reset_quirk is not.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-09-13 11:56:08 -04:00
Priyanka Jain
87d5b22558 MAINTAINERS: Change fsl-qoriq, mpc86xx, mpc85xx maintainers
Change maintainers to Priyanka Jain for fsl-qoriq, mpc85xx

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-09-13 10:14:45 -04:00
Tom Rini
3ee0284a16 Pull request for UEFI sub-system for v2019.10-rc4 (4)
Fixes for the EFI_FILE_PROTOCOL:
 
 * correctly iterate over directories
 * correct Unicode conversion of file names
 * parameter checks
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Merge tag 'efi-2019-10-rc4-4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for v2019.10-rc4 (4)

Fixes for the EFI_FILE_PROTOCOL:

* correctly iterate over directories
* correct Unicode conversion of file names
* parameter checks
2019-09-12 10:35:46 -04:00
Meenakshi Aggarwal
737c016d25 lx2160: Correct serdes frequency print.
Suffix serdes frequency print with MHz

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Hou Zhiqiang
116f75c7b3 armv8: ls1028a: Updated serdes configuration for 0x13BB
In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2

Fixes: 36f50b7523 ("armv8: ls1028a: Add other serdes
		     protocal support")

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Hou Zhiqiang
c9ba88bafc armv8: fsl-layerscape: Fix typo in Layerscape PCIe config entry
The correct config entry is CONFIG_PCIE_LAYERSCAPE and this
typo results in skipping the fixup of Linux PCIe DT nodes.

Also enable the fixup when Layerscape Gen4 controller driver
is enabled.

Fixes: 4da0e52c9d (armv8: fsl-layerscape: fix config dependency
		     for layerscape pci code)

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Florin Chiculita
b9fe1a261a board: lx2160aqds: add support for SerDes protocol 14
Add SerDes1 protocol 14 in the list of supported protocols.
This configuration enables one high-speed 100G port and PCIe x4.

Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Florin Chiculita
065ccdc710 board: lx2160aqds: fix ethernet-phy compatible property
The code that generates the compatible property concatenates the
ethernet phy id and clause-compatible information without
separating them with a comma, resulting into no ethernet phy driver
getting loaded by Linux kernel.
Suffix phy_id_compatible_str with comma to fix this

Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Pankaj Bansal
5d535aa40b board: fsl: lx2160a: implement board_fix_fdt
lx2160a rev1 and rev2 SoC has different pcie controller.
The pcie controller device tree node fields "compatible"
and registers names needs to be updated accordingly

This change in device tree is handled as part of
fdt fixups. These changes would only be applied
if the soc revision is not rev1.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Chuanhua Han
2f2a19757b armv8: fsl-layerscape: Update I2C clock divider
By default, i2c input clock is programmed at
platform clk / 2 in u-boot, but this is not
correct for all the platforms,
Update I2C clock divider's default values as per
SoC (LS1012A, LS1028A, LX2160A and LS1088A).

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Thomas Schaefer
412e25ab5f watchdog: sp805_wdt: add expire_now method
Add sp805_wdt_expire_now function.
expire_now method is required by U_BOOT_DRIVER.

Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Thomas Schaefer
0490cab584 armv8: ls1028a: configure PMU's PCTBENR to enable WDT
The SP805-WDT module on LS1028A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.

Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:42 +05:30
Alex Marginean
a3ce94b602 arm: dts: ls1028a-qds: define the MDIO MUX
Add the device-tree structure describing the MUX in board dts.

QDS board has an on-board RGMII PHY and 4 slots for extension cards.
All these can be accessed over MDIO through a MDIO MUX controlled
over I2C.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 16:15:31 +05:30
Pankaj Bansal
f002b3fa8d board/lx2160a: Fix MC firmware loading for SD boot
During boot, u-boot reads MC, DPL, DPC firmware from SD card
and copies to DDR. Update DDR addresses to which these firmwares
are copied as per memory map of these firmwares on SD-card
so that isolation between the regions of various firmwares
is maintained to avoid geting overwritten.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:11:36 +05:30
Yinbo Zhu
f09d52b4c0 configs/ls1012ardb,lx2160ardb,ls1028ardb: add esdhc hs200 config
Enable CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK and
CONFIG_MMC_HS200_SUPPORT config for
ls1012ardb, ls1012ardb, lx2160ardb
in defconfig file

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:06:29 +05:30
Yinbo Zhu
6f883e501b mmc: fsl_esdhc: Add emmc hs200 support
Add eMMC hs200 mode for ls1028a, ls1012a, lx2160a.
This increases eMMC performance.
Tuning procedure is currently not supported.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:05:38 +05:30
Yinbo Zhu
23da111d5f dts: armv8: add emmc hs200 support for ls1028ardb
Add emmc hs200 support for ls1028ardb

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:04:43 +05:30
Yinbo Zhu
0f021c8bde dts: armv8: add emmc hs200 support for lx2160ardb
Add emmc hs200 support for lx2160ardb

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:04:09 +05:30
Yinbo Zhu
be852314dc dts: armv8: add emmc hs200 support for ls1012ardb
Add emmc hs200 support for ls1012ardb

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:03:10 +05:30
Yinbo Zhu
29009a507c mmc: Kconfig: Add FSL_ESDHC_USE_PERIPHERAL_CLK option
NXP fsl_esdhc controller supports two reference clocks:
platform clock and peripheral clock
Peripheral clock can provide higher clock frequency
which is required to be used for tuning of SD UHS mode
and eMMC HS200/HS400 modes.

Peripheral clock is enabled by default by defining config
option FSL_ESDHC_USE_PERIPHERAL_CLK if eMMC HS200/HS400 modes
are supported.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:02:10 +05:30
Yinbo Zhu
24cb6f2295 fsl-layerscape: Add fsl_esdhc peripheral clock support
Add esdhc peripheral clock support
for NXP layerscape platforms: LS1046ARDB, LS1043ARDB,
LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:00:35 +05:30
Tom Rini
5ba8b12543 Merge tag 'u-boot-rockchip-20190912' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- add idbloader.img target for rockchip tpl+spl;
- usb ehci/ohci: go on process if clock driver don't have clk_enable();
- remove clk_enable() for rockchip clock drivers;
- add boot order for rockpro64
2019-09-11 23:08:34 -04:00
Heinrich Schuchardt
8262578535 efi_loader: parameter checks EFI_FILE_PROTOCOL.SetInfo()
We do not support volume label changes. No parameter checks are needed
here.

When the info for as file is changed the buffer must always contain a file
name.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-09-11 21:51:38 +02:00
Matwey V. Kornilov
326b262419 doc: lion_rk3368: use idbloader.img for rk3368
Makefile now produces ready-to-deploy idbloader.img file.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Matwey V. Kornilov
78af73efa0 doc: rockchip: use idbloader.img for rk3288, rk3328, rk3399
Makefile now produces ready-to-deploy idbloader.img file.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Matwey V. Kornilov
1b0a936b52 rockchip, Makefile: add idbloader.img target
Many Rockchip platforms require the same u-boot deploy procedure
when TPL and SPL both enabled.

The following examples are taken from doc/README.rockchip
and board/theobroma-systems/lion_rk3368/README:

RK3288:

  ./tools/mkimage -n rk3288 -T rksd -d ./tpl/u-boot-tpl.bin out
  cat ./spl/u-boot-spl-dtb.bin >> out
  sudo dd if=out of=/dev/mmcblk0 seek=64

RK3328:

  ./tools/mkimage -n rk3328 -T rksd -d ./tpl/u-boot-tpl.bin idbloader.img
  cat ./spl/u-boot-spl.bin >> idbloader.img
  sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64

RK3368:

  ./tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img
  cat spl/u-boot-spl-dtb.bin >> spl-3368.img
  dd if=spl-3368.img of=/dev/sdb seek=64

RK3399:

  ./tools/mkimage -n rk3399 -T rksd -d ./tpl/u-boot-tpl-dtb.bin out
  cat ./spl/u-boot-spl-dtb.bin >> out
  sudo dd if=out of=/dev/sdc seek=64

Here, we introduce generic idbloader.img target
which is the TPL image followed by the SPL binary.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
c9ec5fe018 rockchip: clean makefile for misc.c
Use obj-$(config) instead of #ifdef $config to make the code looks
clean, and move the misc_init for U-Boot proper only.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
45f8b55eca rockchip: not depends on TPL_BUILD for rk3188 makefile including
The rk3188/Makefile already depends on !TPL_BUILD, so no need to add
this again in parent Makefile, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
445f85fc8e rockchip: clk: rk3399: remove clk_enable()
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
7be113ba79 rockchip: clk: rk3368: remove clk_enable()
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
899c3b3523 rockchip: clk: rk3328: remove clk_enable()
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
c7ed19047e rockchip: clk: rk3288: remove clk_enable()
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
6578db8961 usb: ohci-generic: don't probe fail if there is no clk_enable() ops
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk()
do not return fail if ret value is '-ENOSYS'

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-09-11 16:16:12 +08:00
Kever Yang
54a0c7b2e7 usb: ehci-generic: don't probe fail if there is no clk_enable() ops
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk()
do not return fail if ret value is '-ENOSYS'

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-09-11 16:16:12 +08:00
Kever Yang
86b4a6db68 rockchip: rk3399: dts: add boot order for rockpro64
The rk3399 rockpro64 board can boot from emmc and sdcard.
TODO: add spiflash as boot device.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Jean-Jacques Hiblot
e3e5825d01 usb: musb_hcd: fix compilation error
commit 65c1f9820c8f79f "usb: Add nonblock argument to submit_int_msg"
breaks the musb_hcd driver.
Fixing it by adding the missing argument

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-09-11 10:11:39 +02:00
Michal Suchanek
9dcab2c4d2 dwc2: use the nonblock argument in submit_int_msg
An USB 1.1 keyboard connected to dwc2 through a high-speed hub does not
report status until it changes. With this patch you can enable keyboard
by pressing a key while USB devices are probed. Without a keypress no
state is reported and the probe times out. We don't want to wait for a
keypress or timeout while polling for keypresses so implement an int_msg
nonblock variant that exits early on error.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2019-09-11 10:11:29 +02:00
Michal Suchanek
3437121c03 usb: Add nonblock argument to submit_int_msg
This will be used to implement non-blocking keyboard polling in case of
errors.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2019-09-11 10:11:29 +02:00
Michal Suchanek
50dce8fbf0 usb: storage: submit_int_msg -> usb_int_msg
Use the wrapper as other callers do.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2019-09-11 10:11:29 +02:00
Michal Suchanek
fdd135bf8e usb: usb_submit_int_msg -> usb_int_msg
This aligns naming with usb_bulk_msg and usb_control_msg.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2019-09-11 10:11:29 +02:00
Michal Suchanek
3e816a2424 usb_kdb: only process events successfully received
Causes unbound key repeat on error otherwise.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2019-09-11 10:11:29 +02:00
Tom Rini
001c8ea94a Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Tangier ACPI table fixes
- Support getting high memory size on QEMU x86
- Show UEFI images involved in crash for x86
- EFI loader conventional memory map fix
2019-09-10 08:52:00 -04:00
Tom Rini
3aec234e3f - Add support for dis_u2_susphy_quirk in the xhci-dwc3 driver to fix boot when
a device is plugged only in the OTG capable port for libretech-ac and libretech-cc
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Merge tag 'u-boot-amlogic-20190910' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- Add support for dis_u2_susphy_quirk in the xhci-dwc3 driver to fix boot when
a device is plugged only in the OTG capable port for libretech-ac and libretech-cc
2019-09-10 08:51:17 -04:00
Andy Shevchenko
dd4faa964f x86: tangier: Use spaces over TABs in ASL code
For sake of consistency use spaces over TABs in ASL code.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 16:19:03 +08:00
Andy Shevchenko
980fe1ab2a x86: tangier: Fix off-by-one error when preparing CSRT
Intel iDMA 32-bit controller has 17 bits for the maximum block size value.
Due to nature of the binary number representation the maximum value is
2^17 - 1. The original code misses the latter part in equation.

Fixes: 5e99fde34a ("x86: tangier: Populate CSRT for shared DMA controller")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 16:19:03 +08:00
Andy Shevchenko
0c6352ec2a x86: tangier: Reserve PCI ECAM in motherboard resources
Per PCI firmware specification the ACPI has to reserve the memory
which is defined as PCI ECAM.

Fixes: 39665beed6 ("x86: tangier: Enable ACPI support for Intel Tangier")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 16:19:03 +08:00
Andy Shevchenko
19b6e1ba8c x86: acpi: Annotate struct acpi_table_header with __packed
GCC 9.2 starts complaining about possible pointer misalignment of
pointers to the unpacked (alignment=4) structures in the packed
(alignment=1) ones:

  CC      arch/x86/cpu/tangier/acpi.o
arch/x86/cpu/tangier/acpi.c: In function ‘acpi_create_fadt’:
arch/x86/cpu/tangier/acpi.c:22:37: warning: taking address of packed
member of ‘struct acpi_fadt’ may result in an unaligned pointer value
[-Waddress-of-packed-member]
  22 |  struct acpi_table_header *header = &(fadt->header);

  CC      arch/x86/lib/acpi_table.o
arch/x86/lib/acpi_table.c: In function ‘acpi_create_spcr’:
arch/x86/lib/acpi_table.c:366:37: warning: taking address of packed
member of ‘struct acpi_spcr’ may result in an unaligned pointer value
[-Waddress-of-packed-member]
  366 |  struct acpi_table_header *header = &(spcr->header);

Fix the potential issues by annotating embedded structures with
__packed even though they are packed naturally.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add GCC version number in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 16:17:55 +08:00
Neil Armstrong
b35b807682 usb: xhci-dwc3: Add support for dis_u2_susphy_quirk
This quirk is necessary for the Amlogic GXL SoCs otherwise the
Port 2 PHY doesn't get out of suspend and U-Boot resets the board after:

XHCI timeout on event type 33... cannot recover.
BUG: failure at drivers/usb/host/xhci-ring.c:474/xhci_wait_for_event()!
BUG!

This quirk is also handled in the dwc3 core code, but until the
xhci-dwc3 driver uses the dwc3 core, the quirk must be handled here
to fix USB support on the Amlogic libretech-cc and libretech-ac board
when a device is only plugged in the OTG port.

Cc: Yuri Frolov <crashing.kernel@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Fixes: dc9cdf859e ("usb: dwc3: Add DWC3 controller driver support")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10 10:00:53 +02:00