Commit graph

64035 commits

Author SHA1 Message Date
Neil Armstrong
838c0af9d2 phy: meson-gxl-usb: add set_mode call to force switch to peripheral mode
Add set_mode function in the Amlogic GXL PHYs that will be called by
the arch code to switch PHYs from/to gadget mode.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-20 14:19:10 +02:00
Neil Armstrong
c2b9aa98bf generic-phy: add generic_phy_get_by_node()
Add generic_phy_get_by_node() to get a PHY phandle from a node instead
of a udevice.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[narmstrong: fixed by including ofnode.h in generic-phy.h]
2020-04-20 14:19:10 +02:00
Neil Armstrong
c8ccca921a arm64: dts: meson-gx: add back dmc register range until canvas driver is available
The Linux VPU bindings have changed and dropped the dmc register range.

Add it back in the meson-gx-u-boot.dtsi file until a proper canvas driver
is available.

Fixes: dd5f2351e9 ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-16 16:25:51 +02:00
Neil Armstrong
ae9bf79bed ARM: dts: add missing meson-gxl-s805x-libretech-ac-u-boot.dtsi file
The libretech-ac u-boot.dtsi file is missing to enabled DT nodes changes
to enable Video output on U-Boot.

Fixes: 671b1db8f8 ("arm64: dts: meson-gx: vpu should be probed before relocation")
Reported-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
2020-04-16 09:29:00 +02:00
Heinrich Schuchardt
d2235ee56c configs: correct SMBIOS information for ODROID-C2
CONFIG_SMBIOS_MANUFACTURER="amlogic"
CONFIG_SMBIOS_PRODUCT_NAME="p200"

is incorrect for the ODROID-C2.

Show correct board name and manufacturer in SMBIOS.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-15 18:06:39 +02:00
Heinrich Schuchardt
6da749d8b3 arm: meson: imply DM_RNG
All ARCH_MESON boards have a hardware random number generator. So we should
enable building the RNG driver.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-15 18:06:28 +02:00
Tom Rini
142a07f2a4 Merge branch 'master' of git://git.denx.de/u-boot-marvell
- Misc enhancements to Clearfog, including board variant detection
  (Joel)
- Misc enhancements to Turris Mox, including generalization of the
  ARMADA37xx DDR size detection (Marek)
2020-04-14 08:47:07 -04:00
Marek Behún
c64ac3b318 arm: mvebu: turris_mox: fix PCIe ranges in device tree
Use the new a3700_fdt_fix_pcie_regions function in turris_mox.c so that
MOX boards with 4 GB RAM are fully supported.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
cb2ddb291e arm64: mvebu: a37xx: add device-tree fixer for PCIe regions
In case when ARM Trusted Firmware changes the default address of PCIe
regions (which can be done for devices with 4 GB RAM to maximize the
amount of RAM the device can use) we add code that looks at how ATF
changed the PCIe windows in the CPU Address Decoder and changes given
device-tree blob accordingly.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
4e9eb04c8d arm: mvebu: turris_mox: support devices with RAM > 1 GB
In order to support MOX boards with 2 GB or 4 GB RAM, we use the new
Armada-3700 generic code for memory information structures. This is done
by removing dram_init and dram_init_banksize from turris_mox.c, in order
for the generic, weak definitions to be used.

Also for boards with 4 GB RAM it is needed to increase
CONFIG_NR_DRAM_BANKS to 2 in turris_mox_defconfig.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
a129f64fb0 arm64: mvebu: a37xx: improve code determining memory info structures
Currently on Armada-37xx the mem_map structure is statically defined to
map first 2 GB of memory as RAM region, and system registers and PCIe
region device region.

This is insufficient for when there is more RAM or when for example the
PCIe windows is mapped to another address by the CPU Address Decoder.
In the case when the board has 4 GB RAM, on some boards the ARM Trusted
Firmware can move the PCIe window to another address, in order to
maximize possible usable RAM.

Also the dram_init and dram_init_banksize looks for information in
device-tree, and therefore different device trees are needed for boards
with different RAM sizes.

Therefore we add code that looks at how the ARM Trusted Firmware has
configured the CPU Address Decoder windows, and then we update the
mem_map structure and compute gd->ram_size and gd->bd->bi_dram bank
base addresses and sizes accordingly.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
f075b425a7 arm64: mvebu: armada-8k: move dram init code
Move Armada-8k specific DRAM init code into armada-8k specific
directory.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
c8a185a823 arm: mvebu: turris_mox: sort headers alphabetically
Sort #includes alphabetically, the only exception is common.h, which is
included first in most parts of U-Boot.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
9657841010 arm: mvebu: turris_mox: don't use hardcoded addresses
Use macro MVEBU_REGISTER to access register addresses instead of
hardcoded addresses.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
9e4cdbabac arm: mvebu: dts: turris_mox: fix USB3 regulator
Commit e8e9715df2 requires the USB3 regulator node to have the
enable-active-high property for the regulator to work properly. The
GPIO_ACTIVE_HIGH constant is not enough anymore.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Fixes: e8e9715df2 ("regulator: fixed: Modify enable-active-high...")
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
2b3f2dd1ce arm: mvebu: turris_mox: Setup Linux's device tree before boot
Patch Linux's device tree according to which Mox modules are connected.
Linux's device tree has all possible Mox module nodes preprogrammed, but
in disabled state.

If MOX B, MOX F or MOX G module is present, this code enables the PCI
node.

For the network modules (MOX C, MOX D and MOX E) are present, the code
enables corresponding ethernet and swtich nodes and DSA connections.
For the SFP cage the SFP GPIO controller node and SFP node are also
enabled.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
eddd6f90c9 arm: mvebu: dts: turris_mox: update sdhci properties
With recent changes to the mmc subsystem (chip detect code etc) update
the sdhci node of the Turris Mox device tree.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Marek Behún
b80ca8176d arm: mvebu: turris_mox: Fix early SPI communication
The SPI clock signal changes value when the SPI configuration register
is configured. This can sometimes lead to the device misinterpreting
the enablement of the SPI controller as actual clock tick.
This can be solved by first setting the SPI CS1 pin from GPIO to SPI mode,
and only after that writing the SPI configuration register.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
27f48f7dc4 arm: mvebu: clearfog: Use Pro DT by default
Switch to explicitly using the Pro variant DT, which has been
available since Linux 4.11.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
c5936cc4f8 arm: mvebu: clearfog: move ENV params to Kconfig
Migrate the values for ENV_SIZE and ENV_OFFSET into board specific
Kconfig defaults so they're more accessible for configuration.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
b16d7c3216 arm: mvebu: clearfog: add SPI offsets
Add reasonable default SPI offsets and ENV size when configured to
boot from SPI flash.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
8eccd0dda0 arm: mvebu: clearfog: Unify DT selection paths
Unify the location of DT selection into board_late_init instead of
split between detection and static configuration paths.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
009d4cfcf2 arm: mvebu: clearfog: Add SATA mode flags
The mPCIe slots on ClearFog Pro and ClearFog Base may be alternately
configured for SATA usage.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
8a86308a87 arm: mvebu: clearfog: Add option for 2.5 Gbps SFP
While newer Linux kernels provide autoconfiguration of SFP, provide
an option for setting in U-Boot Kconfig for use prior to booting.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
9f205d658d arm: mvebu: clearfog: initial ClearFog Base variant
Add a unique entry for ClearFog Base variant, reflected in the board
name and adjusted SerDes topology.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
ee26e8539f arm: mvebu: clearfog: use Pro name by default
Make the board version printed indicate the Pro variant default.
Also adjust static name casing to match what is expected for
EEPROM product name to share string constants.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
a8d0aa31bd arm: mvebu: solidrun: remove hardcoded DTS MAC address
Using a consistent hardcoded MAC address from the DTS file causes
issues when using multiple devices on the same network segment.
Instead rely on environment configuration or random generation.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
4f7991ee1c arm: mvebu: fix SerDes table alignment
Tested on Solidrun ClearFog Base. Table alignment was:
 | Lane #  | Speed |  Type       |
 --------------------------------
 |   0    |  3   |  SATA0       |
 |   1    |  0   |  SGMII1      |
 |   2    |  3   |  SATA1       |
 |   3    |  5   |  USB3 HOST1  |
 |   4    |  5   |  USB3 HOST0  |
 |   5    |  4   |  SGMII2      |
 --------------------------------

After the change, it's correctly aligned as:
 | Lane # | Speed |  Type       |
 --------------------------------
 |   0    |   3   | SATA0       |
 |   1    |   0   | SGMII1      |
 |   2    |   5   | PCIe1       |
 |   3    |   5   | USB3 HOST1  |
 |   4    |   5   | PCIe2       |
 |   5    |   0   | SGMII2      |
 --------------------------------

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
cecf38a755 arm: mvebu: clearfog: support multiple SATA boot
Enable distro bootcmd support for additional SATA ports if enabled.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Joel Johnson
bd02fd29f9 arm: mvebu: clearfog: add SCSI to distro bootcmd
Include attempting to boot from SCSI (SATA) devices within generated
board distro bootcmd environment. The reasoning for boot ordering is
that MMC and USB are external and removable, while when a case is in
use, replacing M.2 or mSATA drives requires disassembly. Therefore,
to boot SCSI, [bootable] external media must be removed. If SCSI were
placed before MMC or USB, then removing a bootable SCSI drive to
enable MMC or USB booting would be more difficult.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Chris Packham
ad91fdfff0 arm: mvebu: update RTC values for PCIe memory wrappers
Update the RTC (Read Timing Control) values for PCIe memory wrappers
following an ERRATA (ERRATA# TDB). This means the PCIe accesses will
used slower memory Read Timing, to allow more efficient energy
consumption, in order to lower the minimum VDD of the memory.  Will lead
to more robust memory when voltage drop occurs (VDDSEG)

The code is based on changes from Marvell's U-Boot, specifically:

20cd270407
eb608a7c8d
c4af19ae2b

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Josua Mayer
201a500dec arm: mvebu: clearfog: add scsi target to distro-boot
Support for sata devices via the scsi command is available and already
enabled by default for the Clearfog Base and Pro. This change adds scsi
to the list of boot targets used by distro-boot.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Heinrich Schuchardt
a1dd1fcb6e arm: mvebu: drivers/ddr: remove redundant assignment
The value of local variable ecc is immediately overwritten. So we can
remove the first assignment.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:16:42 +02:00
Josip Kelecic
5e2de83f71 arm: mvebu: dts: Sort Armada series dts alphabetically
Sort the Armada series dts in the Makefile alphabetically
prior to adding new board support.

Signed-off-by: Josip Kelečić <josip.kelecic@sartura.hr>
Reviewed-by: Luka Kovacic <luka.kovacic@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14 13:15:26 +02:00
Chris Packham
236609d93c ddr: marvell: a38x: Allow boards to specify CK_DELAY parameter
For some layouts it is necessary to adjust the CK_DELAY parameter to
successfully complete DDR training. Add the ability to specify the
CK_DELAY in the mv_ddr_topology_map.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2020-04-14 08:59:44 +02:00
Tom Rini
2af31afc7a Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2020-04-13 16:06:51 -04:00
Tom Rini
61819012b6 Merge branch 'master' of git://git.denx.de/u-boot-usb 2020-04-13 16:06:36 -04:00
Tom Rini
8914831860 Merge branch 'next'
Pull in changes that have been pending in our 'next' branch.  This
includes:
- A large number of CI improvements including moving to gcc-9.2 for all
  platforms.
- amlogic, xilinx, stm32, TI SoC updates
- USB and i2c subsystem updtaes
- Re-sync Kbuild/etc logic with v4.19 of the Linux kernel.
- RSA key handling improvements
2020-04-13 11:27:00 -04:00
Tom Rini
36fec02b1f Prepare v2020.04
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-13 11:02:18 -04:00
Ley Foon Tan
3958ef307e arm: socfpga: arria10: Enable cache driver in SPL
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
to enable cache driver in SPL.

This fixed error below in SPL:
cache controller driver NOT found!

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-13 13:49:51 +02:00
Ley Foon Tan
5feb5e3215 arm: dts: arria10: Update dtsi/dts from Linux
Update these 3 files from Linux:.
- socfpga_arria10.dtsi (Commit ID c1459a9d7e92)
- socfpga_arria10_socdk.dtsi (Commit ID d9b9f805ee2b)
- socfpga_arria10_socdk_sdmmc.dts (Commit ID 17808d445b6f)

Change in socfpga_arria10.dtsi:
- Add clkmgr label, so that can reference to it in u-boot.dtsi.

Change in socfpga_arria10-u-boot.dtsi:
- Add compatible and altr,sysmgr-syscon for uboot.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-13 13:49:51 +02:00
Ley Foon Tan
f3fccb12c0 arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
Move Uboot specific properties to *u-boot.dtsi files.
Preparation to sync Arria 10 device tree from Linux.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-13 13:49:51 +02:00
Marek Vasut
8876f89640 ARM: socfpga: Enable DM RTC bootcount on ABB SECU1
Add and enable RTC-backed boot counter on ABB SECU1 platform.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-13 13:49:51 +02:00
Rayagonda Kokatanur
9cadf05958 drivers: usb: host: Add BRCM xHCI driver
Base driver for Broadcom xHCI controllers

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
2020-04-13 13:48:41 +02:00
Kever Yang
2517deafc2 usb: Migrate to support live DT for some driver
Use ofnode_ instead of fdt_ APIs so that the drivers can support live DT.
This patch updates usb_get_dr_mode() and usb_get_maximum_speed() to use
ofnode as parameter instead of fdt offset. And all the drivers who use
these APIs update to use live dt APIs at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-13 13:48:30 +02:00
Kever Yang
0148bbe8f3 usb: ehci-msm: Use dev interface to get device address
Use dev_read_addr_ptr() instead of devfdt_get_addr() so that we can support
live DT.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2020-04-13 13:48:30 +02:00
Kever Yang
5c17030358 usb: dwc3-of-simple: Drop redundant inclding header file
The fdtdec.h is no use in this file, remove the include code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-13 13:48:30 +02:00
Tom Rini
98985791b8 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- Fixes DDR initialization failure on PowerPC boards like P3041DS,
  P4080DS
2020-04-12 08:10:13 -04:00
Tom Rini
67bbc1ecd3 Merge branch '2020-04-11-CI-further-improvements' into next
- Further clean up and improve our Azure/GitLab/Travis CI loops
2020-04-11 11:18:14 -04:00
Simon Glass
4ee7f52781 travis/gitlab/azure: Run cppcheck in parallel
This takes ages to run single-threaded. Adjust it to use all available
processors.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-10 21:36:37 -04:00